Vendor: Obsidian Technology Category: Voltage Reference

Micro Power Bandgap for TSMC 180nm

The OT0120t130 is a 1.2V CMOS micro power CMOS bandgap and current reference cell with sub-µW power dissipation.

TSMC 180nm BCDG2 View all specifications

Overview

The OT0120t130 is a 1.2V CMOS micro power CMOS bandgap and current reference cell with sub-µW power dissipation. Can be utilized as non-precision sleep mode bandgap, allowing a higher powered precision bandgap to be powered down.

Key features

  • Less than 1µW power dissipation.
  • Bandgap untrimmed precision of ±10% over process, temperature, and voltage.
  • 100nA PTAT bias current output.
  • 1.6V-2V operation
  • Power down input.
  • Built in switch for glitchless switching between main and sleep mode bandgaps.
  • Base cell area 0.02mm2 in 0.18µ CMOS.
  • Uses 4 metal layers.

Block Diagram

OT0120t180 block diagram

Applications

  • Micro-power systems
  • Sleep mode bandgap

What’s Included?

  • Verilog model.
  • Metal outline.
  • Spice netlist for LVS.
  • Design review spice files.
  • GDS format layout.
  • Timing files.
  • Integration notes.
  • Production test notes.

Silicon Options

Foundry Node Process Maturity
TSMC 180nm BCDG2 —

Specifications

Identity

Part Number
OT0120t180
Vendor
Obsidian Technology
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about Voltage Reference IP cores

What is Micro Power Bandgap for TSMC 180nm?

Micro Power Bandgap for TSMC 180nm is a Voltage Reference IP core from Obsidian Technology listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Voltage Reference?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Voltage Reference IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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