Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
The low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance…
- TSMC
- 3nm
- N3P
- Pre-Silicon
Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
The low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance…
High-Density eMRAM Compiler TSMC 22ULL
The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering…
Bandgap Voltage Reference, 0.45 V Output, Low PPM/°C, TSMC N3P
Bandgap Voltage Reference, 0.45 V Output The Bandgap Voltage Reference IP is a 1.0 V input, low PPM/°C, 0.45 V reference voltage …
LDO Voltage Regulator, 250 mA, TSMC N3P
LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output The LDO IP is a 1.2V low-quiescent-current adjustable output vol…
LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output The LDO IP is a 1.2V low-quiescent-current adjustable output volt…
256x16 Bits OTP (One-Time Programmable) IP, TSMC 152nm 1.8V/3.3V GP MS Process
The AT256X16T152LP0AA is organized as 256 bits by 16 one-time programmable in 16-bit read and 1-bit program modes.
The ATO00128X8TS055ULP3NA is organized as 128x8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.
1x32 Bits OTP (One-Time Programmable) IP, TSMC 0.18um SiGe BiCMOS 1.8V/3.3V Process
The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP).
768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V Process
The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP).
16Kx33 Bits OTP (One-Time Programmable) IP, TSMC 40LP 1.1V/2.5V Process
The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP).
512x8 Bits OTP (One-Time Programmable) IP, TSMC 12FFC 0.8V/1.8V Process
The ATO00512X8TS012FFC8EA is organized as 512 bits by 8 one-time programmable (OTP).
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power.
Embedded OTP (One-Time Programmable) IP, 512x16 bits for 1.8V/3.3V Logic
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 1280x8 bits for 5V BCD_PLUS
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 256x8 bits for 1.5V/5V BCD
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 48x8 bits for 5V Logic
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 1Kx32 bits for 1.5V/5V/32V HV_MR
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded MTP (Multi-Time Programmable) IP, 8Kx32 bits for 1.5V/5V BCD
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementatio…
Embedded MTP (Multi-Time Programmable) IP, 8Kx8 bits for 1.8V/5V BCD
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementatio…
Embedded OTP (One-Time Programmable) IP, 512x32 bits for 0.8V/1.8V FFC
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being reliable and secure.