This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide …
TSMC CLN6FF Asynchronous Read Two Port Register File Compiler
IGMDLRX01A is an asynchronous read and synchronous write ULVT periphery two port register file compiler (2PRF).
TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps o…
The RAR-eSR-qLR Retention Alternating Regulator combines two regulation sub-components: a high-efficiency switching regulator (eS…
Ultra-low quiescent LDO voltage regulator in TSMC 22ULL
Ultra-low quiescent LDO voltage regulator in TSMC 22ULL
Over-voltage Protection Module to handle direct connection of voltage regulators to a 5V battery using standard 2.5 OD 3.3V devic…
Low-quiescent DC/DC buck converter
Supply active and always-on domains from a single converter.
Nano power DC-DC converter in TSMC 22ULL with ultra-low quiescent current and high efficiency at light load, supporting 1.62V to …
Audio codec with capacitor-less 104 dB dynamic range ADC and 100 dB DAC
The sCOD100-uLP-H1-LR-D.02 is a mixed (analog and digital) Virtual Component containing a stereo ADC, a stereo DAC with headphone…
The sCOD100-uLP-ANC-H1-LR-D.02 is a mixed (analog and digital) Virtual Component containing a stereo ADC, a stereo DAC with headp…
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
9 track Near Threshold Voltage standard cell library at TSMC 55 nm
TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing…
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as s…
Dolphin Technology provides Triple Timer Counter (TTC) IP with three independent timer/counter modules that can each be clocked u…
Bluetooth 5.0 LE,Zigbee, and Sub-GHz Transceiver
The BLE5ZSUBGS40LP RF IP is designed for SMIC 40nm LP Process.
The BLE5T55ULP RF IP is designed for TSMC 55nm ULP Process.
Bluetooth 5.0 LE and Sub-GHz Transceiver
The BLE5SUBGT40ULP RF IP is designed for TSMC 40nm ULP Process.
Ultra-Low Power Fractional PLL IP in in TSMC (12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
Low Power Fractional PLL is a general purpose frequency synthesizer with an input reference frequency range from 10 to 240 MHz an…
Low Power Fractional PLL IP in TSMC(12/16nm FFC, 22nm ULP/ULL, 28nm HPC+)
M31 LPFPLL is a low-power programmable fractional-N (LPF), phase-locked loop (PLL) for frequency synthesis.
Special I/O-eMMC/SDIO in TSMC(22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…