Vendor: VEGA Semiconductor Category: PLL

PLL 3.2GHz

This IP is a phase locked loop which base on TSMC 40nm.

Overview

This IP is a phase locked loop which base on TSMC 40nm. It integrates a Phase Frequency detector (PFD), a Charge Pump (CP), a Low Pass Filter (LPF), a Voltage Control Oscillator (VCO) and other associated blocks. All fundamental building blocks as well as fully programmable dividers are integrated on the core. It is developed as a macro cell for clock generator and frequency synthesizer. The output frequency can be up to 3.2GHz. This IP supports operation voltage is 1.1V.

Key features

  • Process: TSMC 40nm 2.5V/1.1V 1P8M process
  • Metal Required: 6 Layers
  • Input frequency range: 24 MHz
  • Compare frequency range: 4MHz~8Hz
  • VCO operation range: 1GHz~3.4GHz
  • Output frequency range: 2GHz/3.2GHz (1-bit select)
  • Ambient Temperature Range: -40~125°C
  • Single Power supply 1.1V±10%

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 40nm G

Specifications

Identity

Part Number
PLL3P2GHZ_TSMC40LP
Vendor
VEGA Semiconductor
Type
Silicon IP

Provider

Frequently asked questions about PLL IP cores

What is PLL 3.2GHz?

PLL 3.2GHz is a PLL IP core from VEGA Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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