DDR Interface IP Cores for TSMC

DDR Interface IP cores provide the controller, PHY, and calibration technologies required to connect SoCs and ASICs to external DRAM memory devices, enabling high-bandwidth and low-latency memory access for compute-intensive applications.

This category includes IP solutions supporting DDR2, DDR3, DDR4, and DDR5 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, training engines, initialization logic, timing management, ECC support, and signal integrity optimization features designed for reliable operation across advanced semiconductor process nodes.

 
All DDR offers for TSMC
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Compare 140 DDR Interface IP Cores for TSMC from 8 vendors

  • DDR4/3 PHY - TSMC 16FF+GL

    Synopsys, Inc.
    HQ: USA

    The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…

    • Controller + PHY + 1
    • DDR4
    • TSMC
    • 16nm
    • FF+GL
    Part #: dwc_ddr4_ddr3_phy_tsmc16ffpgl Maturity: Production
  • DDR4/3 PHY - TSMC 12FFC18

    Synopsys, Inc.
    HQ: USA

    The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…

    • Controller + PHY + 1
    • DDR4
    • TSMC
    • 12nm
    • FFC
    Part #: dwc_ddr4_ddr3_phy_tsmc12ffc18 Maturity: Production
  • DDR4 PHY - TSMC N7

    Synopsys, Inc.
    HQ: USA

    The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…

    • Controller + PHY + 1
    • DDR4
    • TSMC
    • 7nm
    • N7
    Part #: dwc_ddr4_ddr3_phy_tsmc7ff18 Maturity: Production
  • DDR5/4 PHY V2 - TSMC N7

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 7nm
    • N7
    Part #: dwc_ddr54_phy_v2_tsmc7ff18 Maturity: Production
  • DDR5/4 PHY V2 - TSMC N6

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 6nm
    • N6
    Part #: dwc_ddr54_phy_v2_tsmc6ff18 Maturity: Production
  • DDR5 PHY - TSMC N4P

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 4nm
    • N4P
    Part #: dwc_ddr5_phy_tsmc4ffp12 Maturity: Production
  • DDR5 PHY - TSMC N3P

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 3nm
    • N3P
    Part #: dwc_ddr5_phy_tsmc3pff12 Maturity: Production
  • DDR5 MRDIMM2 PHY - TSMC N3P

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 3nm
    • N3P
    Part #: dwc_ddr5_mrdimm2_phy_tsmc3pff12 Maturity: Production
  • DDR5 PHY - TSMC N3E

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 3nm
    • N3E
    Part #: dwc_ddr5_phy_tsmc3eff12 Maturity: Production
  • DDR5 MRDIMM2 PHY - TSMC N2P

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 2nm
    • N2P
    Part #: dwc_ddr5_mrdimm2_phy_tsmc2p12 Maturity: Production
  • DDR5/4 PHY - TSMC 16FFC

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 16nm
    • FFC
    Part #: dwc_ddr54_phy_tsmc16ffc Maturity: Production
  • DDR5/4 PHY - TSMC 12FFC

    Synopsys, Inc.
    HQ: USA

    The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 12nm
    • FFC
    Part #: dwc_ddr54_phy_tsmc12ffc Maturity: Production
  • DDR5 PHY in TSMC (N3E, N5)

    Synopsys, Inc.
    HQ: USA

    The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…

    • Controller + PHY + 1
    • DDR5
    • TSMC
    • 3nm
    • N3E
    Part #: dwc_ddr5_phy_tsmc Maturity: Production
  • DDR4 multiPHY in TSMC (28nm)

    Synopsys, Inc.
    HQ: USA

    The Synopsys DDR4 multiPHY is a physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- ch…

    • Controller + PHY + 1
    • DDR4
    • TSMC
    • 28nm
    • HPC+
    • Available on request
    Part #: dwc_ddr4_multiphy_tsmc Maturity: Production
  • 7 way DDR combo

    Aragio Solutions
    HQ: USA

    The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calib…

    • Controller
    • TSMC
    • 16nm
    • Silicon Proven
    Part #: RGO_TSMC16_18V15_FFC_25C_DDR4_7WC Maturity: Production
  • 7 way DDR combo

    Aragio Solutions
    HQ: USA

    The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calib…

    • Controller
    • TSMC
    • 12nm
    • FFC
    • Silicon Proven
    Part #: RGO_TSMC12_18V15_FFC_25C_DDR4_7WC Maturity: Production
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