How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Aragio Solutions
Category:
DDR
7 way DDR combo
The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calib…
Overview
The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and the DDR voltage reference cell providing both single-ended and differential signaling for LPDDR2, LPDDR3, LPDDR4, DDR3, DDR3L, DDR3U, and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key features
- Full DDR4 capability
- Data rates – 1600 MT/s, 1866 MT/s, 2133 MT/s, 2400 MT/s
- Full DDR3 / DDR3L / DDR3U capability
- Data rates – 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s
- Full LPDDR4 capability
- Data rates – 1066 MT/sec, 2400 MT/sec, 3200 MT/sec, 4266 MT/sec
- Full LPDDR3 capability
- Data rates – 1333 MT/sec, 1600 MT/sec
- Full LPDDR2 capability
- Data rates – 466 MT/sec, 1066 MT/sec
- User programmable drive strength
- DDR3 – ZOUT = 34 / 40 ?
- DDR4 – ZOUT = 34 / 48 ?
- LPDDR2 – ZOUT = 34 / 40 / 48 / 60 / 80 ?
- LPDDR3 – ZOUT = 34 / 40 ?
- LPDDR4 – ZOUT = 40 / 48 / 60 / 80 / 120 / 240 ?
- User programmable on-die termination
- DDR3 – 120 / 60 / 40 / 30 / 24 / 20 / 17 ?
- DDR4 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
- LPDDR3 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
- LPDDR4 – 240 / 120 / 80 / 60 / 48 / 40 / 34 ?
What’s Included?
- Final deliverables for the Licensed Product do not include test chip,
- silicon verification and characterization results, but shall include:
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 16nm | 16nm 160 nm | Silicon Proven |
Specifications
Identity
Part Number
RGO_TSMC16_18V15_FFC_25C_DDR4_7WC
Vendor
Aragio Solutions
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is 7 way DDR combo?
7 way DDR combo is a DDR IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.