Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
Clock and Data Recovery of HDB3/B3ZS coded signals
An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.
TSMC N5A SD/eMMC PHY AG2 Platform
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3P SD/eMMC PHY North/South Poly Orientation MS add-on
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3P SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3E SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3A SD/eMMC PHY AG2 North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
A 2Gbps LVDS Tranceiver in TSMC 28nm This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power …
Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN28HPL
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 SERDES PHY on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Low Power PCIe Gen3 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN12FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).