TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
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Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter …
Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter …
TSMC N3E 1.2V/1.8V OSC METAL STACK ADD ON
Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter …
Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter …
Synopsys offers low jitter Programmable Crystal Oscillator that supports 5 MHz to 50 MHz, with optimized design to reduce jitter …
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