Overview
High end consumer and professional applications require crystals with a minimum number of external components. These applications typically operate under severe noise environment of large digital video processing chips. A standard crystal oscillator pad provided in commodity libraries induces high noise and jitter.
Analog Bits has developed a unique Crystal Oscillator macro based on a proprietary architecture that is in volume production in several high end graphics and multi-media applications. This differentiated architecture has earned outstanding reviews on high volume production boards.
Crystal Pad Electrical Characteristics Description Symbol Min Typ Max Units Frequency Range (crystal mode) 18 40 MHz Frequency Range (bypass mode) 0 250 MHz Rise time tR 40 80 ps Fall time tF 40 80 ps Output Duty Cycle tDO 40 50 60 % Lock Time - Cold Boot tLOCK(COLD) TBD ms Lock Time - Warm Boot tLOCK(WARM) TBD µs Random Jitter (see NOTE2) RJ ps-RMS - Low current mode 0.65 - High current mode 0.58 Time Interval Error (see NOTE3) TIE TBD ps Area (100um [X] by 85.02um [Y]) A 0.0085 sq.mm Total Power (unloaded) (see NOTE1) P mW - Low current mode 4.5 - Nominal current mode 6.9 - High current mode 9.3 Output Load CL 50 fF Operating junction temperature Tj -40 25 125 C Digital power supply VDD 0.675 0.75 0.825 V Analog power supply VDDA 1.62 1.8 1.98 V EM Temperature (see NOTE4) TEM 105 C NOTE1: The power is achieved with appropriate XGAIN settings for a 38.4MHz crystal with ESR=30ohm, shunt capacitance=3pF, load capacitance=12pF.
NOTE2: Integration band of 10kHz to Nyquist, with 38.4MHz crystal with appropriate XGAIN settings for a 38.4MHz crystal with ESR=30ohm, shunt capacitance=3pF, load capacitance=10pF.
NOTE3: With 5mV supply noise NOTE4: EM is verified at 105C for 10 years lifetime limit.
Table 1: Electrical Characteristics of Crystal Pad
Learn more about Oscillator IP core
In this paper, we present a flexible ring oscillator IP designed for a 40nm CMOS technology, whose oscillation frequency can be chosen from 200kHz to 20MHz. It was developed using a new design approach, in which analog IPs are designed from scratch to be flexible, employing modular blocks that can be easily customized. The IP is silicon proven. It works with a supply voltage of 1.2V and features 5% frequency accuracy, occupying an area of 0.0022mm2.
This article reviews the functional-safety attributes of Classical CAN and CAN FD, then explains how CAN XL preserves and extends them. It also discusses higher-layer safety protocols, fault-tolerant CAN XL controller implementations, and CANsec, the CAN XL security extension inspired by the MACsec model. Finally, it highlights how the CAST CAN XL controller IP and CANsec acceleration IP can support the efficient deployment of safety- and security-capable in-vehicle networks.
This article outlines Key ASIC R&D team's upcoming PLL suitable for high-speed SerDes having ultra low jitter with LC- tank VCO, and supporting up to 16 GHz output clock to sample the data.
This article outlines our R&D team's upcoming PLL suitable for high-speed SerDes having ultra low jitter with LC- tank VCO, and supporting up to 16 GHz output clock to sample the data.
How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.
Agile Analog’s tamper detection IP is a comprehensive set of sensors and monitors designed to detect a wide variety of physical attacks and side-channel attacks (SCAs). T
