The low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking or fine tuning on-the-fly. The PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by and operational power.
PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 10 300 MHz Post-Divide Reference frequency FPFD 5 7.5 MHz VCO Frequency FVCO 2000 4000 MHz Output Frequency FOUT 30 2000 MHz Output Duty Cycle tDO 48 52 % Area A 0.013 sq. mm Total Power IDD 4 mA Operational Voltage (Digital) VDIG 0.72 0.8 0.88 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range
