SMIC IP Cores

This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to reach 10-bit resolution.

• 10 Bit
• SMIC
• 180nm
• G

The present IP is a RC oscillator with internal R and C to generate 32±20%KHz clock.

• SMIC
• 130nm
• G

The USB11PHY is an IP version of USB transceiver.

• UCIe 1.1
• SMIC
• 150nm
• LV

This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.

• 12 Bit
• SMIC
• 130nm
• G
• Silicon Proven

The present IP is a VCC Detector (VDT) circuit with normal operating voltage ranging from 1.08V ~1.32V.

• SMIC
• 130nm
• G

Targeted in SMIC 0.13um 3.3v Logic process, current design of Power Regulator is to provide 1.2v power supply which is regulated …

• SMIC
• 130nm
• G

The present IP is a Power On Reset (POR) circuit without any external resistor or capacitor.

• SMIC
• 130nm
• G

This PLL is designed for audio clock generation.

• SMIC
• 130nm
• G

This IP is a programmable Analog PLL suitable for high speed clock generation.

• SMIC
• 130nm
• G

This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.

• SMIC
• 130nm
• G

This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.

• SMIC
• 130nm
• G

The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.

• 12 Bit
• SMIC
• 130nm
• G

This IP is a programmable Analog PLL suitable for high speed clock generation.

• SMIC
• 130nm
• G

The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.

• SMIC
• 130nm
• G

The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word.

• SMIC
• 130nm
• G

Present Power on Reset generates system reset pulses (POR18) when 1.8V power supplier (VIN18) is turned on.

• SMIC
• 130nm
• G

This IP is a Low-Dropout (LDO) 5V to 3.3V power regulator in SMIC 0.13μm 3.3V/1.2V Logic process.

• SMIC
• 130nm
• G

Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…

• SMIC
• 130nm
• G

Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.8v power supply which is regul…

• SMIC
• 130nm
• G

This IP is a programmable Analog PLL suitable for high speed clock generation.

• SMIC
• 130nm
• G