Overview
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.8v power supply which is regulated from the single 3.3v supply. This IP can work in the LDO mode, which means the 3.3v supply input can drop to 1.65v at minimum, accordingly in the LDO mode, output voltage will drop by Vdrop from the input supply voltage. The minimum output current driver capability is 300mA. This IP cannot be used alone. It must be used together with another VeriSilicon IP, S13V33_PRG_05 because the reference voltage and current bias should come from S13V33_PRG_05. This particular physical IP has the scaled up version of S13V33_PRG_04B which is designed to be used in foundry’s 0.11um (90% shrink) process.
Learn more about LDO Voltage Regulator IP core
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