Ultra-short reach SerDes with 500 Gbit/s throughput
High-density, low-power SerDes IP delivering 500 Gbit/s throughput for in-package and multi-chip module interconnects, without a silicon interposer.
- GlobalFoundries
- 12nm
- LP
- Available on request
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Ultra-short reach SerDes with 500 Gbit/s throughput
High-density, low-power SerDes IP delivering 500 Gbit/s throughput for in-package and multi-chip module interconnects, without a silicon interposer.
JESD204b Deserializer PHY - GF 22nm FDX
JESD204b Deserializer PHY, 6.375 Gbps up to 12.5 Gbps per lane - GF 22nm FDX
JESD204b Serializer PHY - GF 22nm FDX
JESD204b Serializer PHY, 6.375 Gbps up to 12.5 Gbps per lane
UHF RFID EPC Gen2 physical interface
130GF _G2PHY_02 is the IP intended for use in passive UHF transponder applications.
PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification.
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ended
16 Gbps APXpress PHY with 4-tap Tx FIR, CTLE, 12-tap DFE, and 30 dB IL target. Part of the Inova APXpress ecosystem
Universal Chiplet Interconnect Express PHY IP - GLOBALFOUNDRIES® 22FDX®
UCIe PHY IP with X16 data width for standard package and up to 8 Gbit/s per pin data rate
A 32Gbps SerDes PHY in GlobalFoundries 22FDX withlow-jitter, half-rate tran mission, and a configurable CTLE-based receiver.
USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
High-performance, low-latency PHY for D2D connectivity
V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates.
V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections.
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS transmitter.
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
A transmitter for LVDS with a physical layer IP.
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in GF 65/55LPe
The HDMI receiver PHY (Physical layer), a single-port IP core, fully conforms with HDMI 1.4's requirements.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in GF 65/55LPe
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DV…
This IP supports operational data rates 80Mbps to 1.5Gbps per One lane for HS mode, and up to 10Mbps for LP modes transfer rates.
MIPI DPHY & LVDS Transmit Combo on GF55LPe
This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications.