Vendor: Synopsys, Inc. Category: Single-Protocol PHY

PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)

The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…

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PCIe Gen2 GlobalFoundries 12nm LP Available on request View all specifications

Overview

The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s PCI Express (PCIe®) designs while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage, and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor
and test for signal integrity without the need for expensive test equipment. This provides on-ch°ip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

Key features

  • Physical coding sublayer (PCS) block with PIPE interface
  • Supports PCIe power management features, including L1 substate
  • Power gating for lowest standby power
  • Low active power using voltage mode TX with under drive supply options
  • The multi-channel PHY macro with single clock and control core for higher density
  • Supports both internal and external reference clock inputs
  • PIPE bifurcation as well as PHY macro aggregation for x8 and x16 PHY configurations
  • Multi-featured transmitter and receiver equalization
  • Each lane in a multi-channel PHY macro contains its own pseudo random bit sequencer (PRBS) for internal and external loopbacks, used to verify TX and RX circuitry
  • Each channel is fully controllable via the test access port (TAP) and core interface
  • The PHY IP is capable of mapping the signal eye, and outputs the signal statistics via JTAG interface

Benefits

  • Compliant with the PCI Express 2.1, 1.1, and PIPE specifications
  • x1, x2, x4, x8, x16 lane configurations with bifurcation
  • PCIe L1 substate power management
  • Supports power gating and power island
  • Embedded bit error rate tester (BERT) and internal eye monitor
  • ATE test vectors for complete, at-speed production testing
  • Pseudo random bit sequencer (PRBS) generation and checker
  • IEEE 1149.6 AC JTAG Boundry Scan
  • Beaconing, receiver detection and electrical idle features
  • Supports -40°C to 125°C junction temperatures

Applications

  • Desktops, laptops, workstations and servers
  • Embedded systems and set-top boxes
  • Network switches and routers
  • Enterprise computing and storage networks
  • Consumer portable devices
  • Graphics devices
  • Wireless devices

What’s Included?

  • Verilog models
  • Liberty timing views (.lib)
  • LEF abstracts (.lef)
  • CDL netlist (.cdl)
  • GDSII
  • ATPG models
  • IBIS-AMI models
  • HSPICE models for TX and RX
  • Documentation

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP Available on request

Specifications

Identity

Part Number
dwc_pcie2phy_gf
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen2

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about Single-Protocol PHY IP core

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Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

Frequently asked questions about Single-Protocol PHY IP

What is PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)?

PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm) is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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