Vendor: Synopsys, Inc. Category: Single-Protocol PHY

SD/eMMC in GF (12nm)

To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and…

GlobalFoundries 12nm LP Available on request View all specifications

Overview

To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for embedded mass-storage flash memory (eMMC) and removable flash memory card (SD Card), targeting a range of applications. The Synopsys SD/eMMC PHY IP, compliant with the latest JEDEC and SD specifications, is a fully integrated hard macro with high-speed IOs and Delay Locked Loop (DLL)/delay lines. Optimized for power and area, the PHY IP is fully verified and configurable for easy integration into application processors. The PHY IP and Synopsys SD/eMMC Host Controller IP offer a fully verified solution that designers can use to integrate the latest embedded and removable memory functionality into their application processor, while speeding time-to-market.

Key features

  • Compliant with eMMC5.1 and SD 6.0
  • Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1
  • Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS)
  • Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device
  • Ease of integration
  • Fully optimized, compliant and interoperable SD/eMMC solution
  • Flexible configuration to target both 4-bit and 8-bit applications
  • Consistent delay line granularity/resolution across process corners
  • Electrically compliant drivers
  • Future proof design

Benefits

  • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
  • Fully integrated hard macro with high speed IOs and DLL/delay lines
  • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
  • Easy to integrate with the highly optimized Synopsys DesignWare SD/eMMC Host Controller IP, providing a complete low risk solution
  • Optimized for area
  • Scalable and low pin count solution
  • Ultra-low-power operation

Applications

  • Mobile
  • Multimedia
  • Automotive
  • Internet of Things (IoT)

What’s Included?

  • Databook
  • Behavioral model
  • LEF file
  • .LIB file
  • GDSII layout database

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP Available on request

Specifications

Identity

Part Number
dwc_sd_emmc_gf
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about Single-Protocol PHY IP core

Synopsys Advances Virtual Development of Next-Generation Automotive and Physical AI Applications with Infineon AURIX™ RC1 Microcontroller Family

Synopsys extended its long-standing collaboration with Infineon to deliver a Synopsys Virtualizer™ Development Kit (VDK) supporting Infineon’s AURIX™ RC1 microcontroller (MCU) family. The VDK equips automotive engineering teams with a virtual prototype of the AURIX™ RC1 MCU, Infineon’s new scalable computing platform for software-defined vehicle (SDV) and Physical AI applications.

Frequently asked questions about Single-Protocol PHY IP

What is SD/eMMC in GF (12nm)?

SD/eMMC in GF (12nm) is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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