Vendor: Synopsys, Inc. Category: Custom

Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)

The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interface…

GlobalFoundries 12nm LP Available on request View all specifications

Overview

The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The lowlatency, low-power, and compact PHY supports NRZ and PAM-4 signaling from 2.5G to 112G data rates and is compliant with the OIF CEI-112G and CEI-56G standards for extra- short reach (XSR) links. The XSR PHY offers flexible layout for maximum bandwidth per die-edge by allowing placement of the square macros along all edges of the die. It deploys 16-lane transmit and receive macros for optimized segmentation on the multiple dies. The robust DLL-based clock forwarded architecture enables high energy efficiency while supporting reliable links of up to 50 millimeters for large MCMs. The PHY enables multi-die connectivity over organic substrates, which helps reduce packaging costs without requiring advanced interposer-based packaging over shorter distances. The embedded bit error rate (BER) tester and nondestructive 2D eye monitor capability provide on-chip testability and visibility into channel performance. Besides the PMA and PMD, the PHY includes a raw-PCS to facilitate the interface with the on-chip network, regardless of the existing networking protocol. The XSR IP is combined with Synopsys’ comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast and reliable integration into SoCs

Key features

  • Offers leading performance, power, and area / beachfront per terabit
  • Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
  • Targeting the OIF XSR standards: CEI-112G and CEI-56G
  • Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
  • Physical Medium Dependent (PMD) soft-layer includes power sequencing and calibration engines
  • Implements RX scope and PRBS and pattern generator, matcher and error counter for BERT testing
  • Non-destructive 2D eye monitor capability can be performed during mission-mode operation
  • Shared PLLs allow maximum energy efficiency
  • Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal path

Benefits

  • 16-lane TX and RX square macros for placement in any edge of the die
  • Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
  • Implements NRZ and PAM-4 signaling
  • Meets the performance, efficiency and reliability requirements of die-to-die interconnects
  • Robust DLL-based, clock forwarded architecture minimizes complexity and power dissipation
  • Linear equalization and T-Coils in RX and TX allow compliance to XSR links up to 50mm for large MCM designs
  • Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
  • Targeting the OIF CEI-112G and CEI- 56G standards for XSR links

Applications

  • Hyperscale data center
  • Enterprise and campus networks
  • Cloud computing/networking
  • Service provider networks
  • Artificial intelligence and machine learning

What’s Included?

  • Verilog models and test bench
  • Protocol-specific test bench
  • Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
  • GDSII
  • IP-XACT XML files with register details
  • ATPG models
  • IBIS-AMI models
  • Documentation

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP Available on request

Specifications

Identity

Part Number
dwc_d2d_sr112_phy_gf
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about Custom IP core

Frequently asked questions about Custom Die-to-Die IP cores

What is Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)?

Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm) is a Custom IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries Available on request.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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