Vendor: SmartDV Category: Ethernet

ETHERNET CYCLIC FEC IIP

ETHERNET CYCLIC FEC core is compliant with IEEE Standard 802.3.2018 Ethernet specification.Through its compatibility, it provides…

Overview

ETHERNET CYCLIC FEC core is compliant with IEEE Standard 802.3.2018 Ethernet specification.Through its compatibility, it provides a simple interface to a wide range of low-cost devices. ETHERNET CYCLIC FEC IIP is proven in FPGA environment.The host interface of the ETHERNET CYCLIC FEC can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.

ETHERNET CYCLIC FEC IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with ETHERNET specification.
  • Supports Full IEEE Standard 802.3.2018 Ethernet cyclic FEC functionality.
  • This FEC(Forward Error correction) methodology implements the (2112 , 2080) binary cyclic code is shortened from the cyclic Fire code (42987, 42955).
  • Supports FEC of 32 bits parity bits.
  • This FEC can correct up to 11-bit burst error.
  • Supports the pipelined mechanism for the error correction.

Block Diagram

ETHERNET CYCLIC FEC IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The ETHERNET CYCLIC FEC interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
ETHERNET CYCLIC FEC IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Ethernet IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Ethernet IP cores

What is ETHERNET CYCLIC FEC IIP?

ETHERNET CYCLIC FEC IIP is a Ethernet IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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