Ethernet 200G,400G Verification IP

The Ethernet 200G,400G Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet 200G,400G interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet 200G,400G Verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

Ethernet 200G,400G Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Ethernet 200G,400G Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports 200G,400G interfaces as per the specifications defined in IEEE 802.3bs
• Supports 200GMII and 400GMII
• Supports 200GXS and 400GXS
• 200GBase_KR8
• 200GBase_KR4
• 200GBase_KR2
• 400GBase_KR4
• 400GBase_KR8
• 400GBase_KR16
• Supports CDAUI_16
• Supports CDMII
• Supports FEC
• Supports scrambler
• Supports backplane auto-negotiation
• Supports Link training
• Supports Pause frame generation and detection.
• Supports MDIO slave and master model as per Clause 22 and Clause 45
• Glitch insertion and detection
• PCS to Serdes interface supports all widths
• Supports CDR for serial protocols
• Supports G.999.1 Interface
• Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
• Full support for IEEE 1588-2002 and IEEE 1588-2008
• Supports the following Upper layer protocols:
• IPV4
• IPV6o TCP
• UDP
• ICMP
• ARP
• GRE
• NVGRE
• VXLAN
• PPPOE
• EAPoL
• FCOE
• RARP
• IPsec
• MACSEC
• Wake on LAN
• Slow protocol
• Supports IP in IP
• Supports Q in Q
• Ethernet Verification IP comes with complete UNH Test suite
• Supports all types of TX and RX errors insertion/detection at each layer.
• Oversize, undersize, inrange, out of range Packet size errors
• Missing SPD/EPD/SFD framing errors
• SFD on wrong lane
• CRC Error
• Lane skew insertion
• Invalid /D/ and /K/ character injection
• Variable preamble and IPG insertion
• Invalid block code insertion
• Sync bit corruption
• FEC error injection
• Scrambler error injection
• Comes with Tx BFM,Rx BFM, and Monitor.
• Monitor supports detection of all protocol violations.
• Built in coverage analysis.
• Status counters for various events in bus

• Faster testbench development and more complete verification of Ethernet 200G,400G designs
• Easy to use command interface simplifies testbench control and configuration of TX and RX
• Simplifies results analysis
• Runs in every major simulation environment

• Complete regression suite (UNH) containing all the Ethernet 200G,400G testcases.
• Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.