Vendor: iSTART-TEK Inc. Category: Monitoring

eFlash BIST IP

Implement all recommendation test items for hight test coverage The BIST can realize all eFlash testing items, covering UMC’s 40n…

Overview

Implement all recommendation test items for hight test coverage

The BIST can realize all eFlash testing items, covering UMC’s 40nm and 55nm processes, as well as SST’s 0.11um and 0.18um processes, and customized embedded eFlash IP wafer software testing and final testing. The BIST features a flexible serial interface, reducing the need for IC test pins and increasing testing flexibility. All testing functions can be individually activated or deactivated, and it provides a diagnostic mode to test memory defect addresses. Additionally, iSTART-TEK’s BISR can record the addresses of eFlash faults and use redundancy features to replace faulty eFlash, thereby improving the yield of eFlash chip products. 

Interface

  • JTAG
  • IEEE 1149.7
  • SPI

Key features

  • Support generating ATE STIL/WGL format
  • Implement all recommendation test items for high test coverage
  • All test item can be configurable
  • Timing parameters can be adjusted
  • Provide users with repairing mode to increase yield
  • Diagnosis mode

Applications

  • Automotive
  • Security
  • White goods
  • MCU
  • IoT
  • Smartcards
  • Wearables
  • Gaming

Specifications

Identity

Part Number
eFlash BIST IP
Vendor
iSTART-TEK Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Taiwan (R.O.C)

Learn more about Monitoring IP core

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Same Chip, Two Destinies: How Power Profiles Improve With On-Chip Monitoring

What happens to critical power-related considerations when the same chip is handled two different ways, with or without visibility from within? This article begins by examining how the absence of on-chip monitoring impacts peak power, average power, and Di/Dt noise (rate of current change), as illustrated in the diagram below and the subsequent discussion. It then details how these aspects change when in-chip telemetry is available.

Runtime Energy Monitoring for RISC-V Soft-Cores

The authors propose a holistic approach to monitor energy consumption at runtime without the need of running complex (micro-)architectural models. Their approach is based on a measurement board coupled with a FPGA-based System-on-Module.

Frequently asked questions about system monitoring IP cores

What is eFlash BIST IP?

eFlash BIST IP is a Monitoring IP core from iSTART-TEK Inc. listed on Semi IP Hub.

How should engineers evaluate this Monitoring?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Monitoring IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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