eFlash BIST IP
Implement all recommendation test items for hight test coverage The BIST can realize all eFlash testing items, covering UMC’s 40n…
Overview
Implement all recommendation test items for hight test coverage
The BIST can realize all eFlash testing items, covering UMC’s 40nm and 55nm processes, as well as SST’s 0.11um and 0.18um processes, and customized embedded eFlash IP wafer software testing and final testing. The BIST features a flexible serial interface, reducing the need for IC test pins and increasing testing flexibility. All testing functions can be individually activated or deactivated, and it provides a diagnostic mode to test memory defect addresses. Additionally, iSTART-TEK’s BISR can record the addresses of eFlash faults and use redundancy features to replace faulty eFlash, thereby improving the yield of eFlash chip products.
Interface
- JTAG
- IEEE 1149.7
- SPI
Key features
- Support generating ATE STIL/WGL format
- Implement all recommendation test items for high test coverage
- All test item can be configurable
- Timing parameters can be adjusted
- Provide users with repairing mode to increase yield
- Diagnosis mode
Applications
- Automotive
- Security
- White goods
- MCU
- IoT
- Smartcards
- Wearables
- Gaming
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about system monitoring IP cores
What is eFlash BIST IP?
eFlash BIST IP is a Monitoring IP core from iSTART-TEK Inc. listed on Semi IP Hub.
How should engineers evaluate this Monitoring?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Monitoring IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.