Vendor: Codasip Category: CPU

Compact, efficient 64-bit RISC-V processor with 5-stage pipeline

The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large addres…

Contact Provider Request Datasheet
RISC-V View all specifications

Overview

The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two versions.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.

Key features

  • 64-bit RISC-V core
    • H50X supports RV64IMC
    • H50XF supports RV64IMCF
  • Fully parallel multiplier
  • 5-stage pipeline
  • Dynamic Branch Predictor
  • RISC-V mode support:
    • Machine, User
  • Internal interrupt controller
    • Up to 256 sources
  • FPU (H50F)
  • Optional instruction and data tightly coupled memories (TCM)
  • Optional 8 or 16 PMP regions
  • Optional L1 data and instruction caches
  • On-chip debugger
    • JTAG and RISC-V Debug module

Benefits

  • Large address space
    • 64-bit addressing
  • Flexibility
    • Wide choice of configuration options.
  • Customization
    • Ability to create custom RISC-V extensions to optimise performance
    • Efficient architectural exploration of custom extensions with Studio
    • Automatic HDK and SDK generation from Studio
    • Rigorous verification of modified H50X(F) core using UVM

Applications

  • Applications that need to access more than 4GB address space, in application areas like SSD and enterprise storage, or MAC layer protocol processing in wireless networking.

What’s Included?

  • Human-readable and structured RTL in either:
    • Verilog
    • VHDL
    • System Verilog
  • Hardware development kit (HDK)
    • Synthesis scripts
    • Simulation testbenches
    • Debug support
  • Software development kit (SDK)
    • LLVM C-compiler
    • Assembler, Disassembler, Linker
    • Instruction-accurate simulator
    • Cycle-accurate simulator
    • Profiler
    • LLDB Debugger
    • OpenOCD

Specifications

Identity

Part Number
Codasip H50(F)
Vendor
Codasip
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Codasip
HQ: Germany
Contact Codasip

Learn more about CPU IP core

A formal-based approach for efficient RISC-V processor verification

In this article, we go through a formal-based, easy-to-deploy RISC-V processor verification application. We show how, together with a RISC-V ISA golden model and RISC-V compliance automatically generated checks, we can efficiently target bugs that would be out of reach for simulation.

Efficient Verification of RISC-V processors

Processor verification, however, is never trivial but requires combining the strengths of multiple verification techniques. This technical paper considers how to efficiently verify a RISC-V processor using a multi-layered approach known as the Swiss cheese model adapted from the world of avionics.

Announcing Arm AGI CPU: The silicon foundation for the agentic AI cloud era

For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.

Frequently asked questions about CPU IP cores

What is Compact, efficient 64-bit RISC-V processor with 5-stage pipeline?

Compact, efficient 64-bit RISC-V processor with 5-stage pipeline is a CPU IP core from Codasip listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP