Vendor: Codasip Category: CPU

Compact, efficient 64-bit RISC-V processor with 5-stage pipeline

The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large addres…

RISC-V View all specifications

Overview

The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two versions.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.

Key features

  • 64-bit RISC-V core
    • H50X supports RV64IMC
    • H50XF supports RV64IMCF
  • Fully parallel multiplier
  • 5-stage pipeline
  • Dynamic Branch Predictor
  • RISC-V mode support:
    • Machine, User
  • Internal interrupt controller
    • Up to 256 sources
  • FPU (H50F)
  • Optional instruction and data tightly coupled memories (TCM)
  • Optional 8 or 16 PMP regions
  • Optional L1 data and instruction caches
  • On-chip debugger
    • JTAG and RISC-V Debug module

Benefits

  • Large address space
    • 64-bit addressing
  • Flexibility
    • Wide choice of configuration options.
  • Customization
    • Ability to create custom RISC-V extensions to optimise performance
    • Efficient architectural exploration of custom extensions with Studio
    • Automatic HDK and SDK generation from Studio
    • Rigorous verification of modified H50X(F) core using UVM

Applications

  • Applications that need to access more than 4GB address space, in application areas like SSD and enterprise storage, or MAC layer protocol processing in wireless networking.

What’s Included?

  • Human-readable and structured RTL in either:
    • Verilog
    • VHDL
    • System Verilog
  • Hardware development kit (HDK)
    • Synthesis scripts
    • Simulation testbenches
    • Debug support
  • Software development kit (SDK)
    • LLVM C-compiler
    • Assembler, Disassembler, Linker
    • Instruction-accurate simulator
    • Cycle-accurate simulator
    • Profiler
    • LLDB Debugger
    • OpenOCD

Specifications

Identity

Part Number
Codasip H50(F)
Vendor
Codasip
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Codasip
HQ: Germany

Learn more about CPU IP core

Codasip announces strategic pivot and divestiture

Codasip today announced a strategic evolution of its business to focus on the rapidly growing need for cyber-resilient semiconductor architectures and semiconductor System on Chips (SoCs). In conjunction with this change, Codasip is also announcing the divesture of its low-end RISC-V processor design business to a public US semiconductor company.

Codasip board initiates an expedited process to sell the company

Codasip, the European RISC-V leader, announced today an accelerated process to sell the company. Codasip has been awarded several grants and equity funding from various bodies of the European Union (EU) and national authorities totaling over €119 million, most of which is still to be received by the company in due course. In addition, the company estimates the follow-on phases of the grants will total a further €210 million for a total of €329 million, and the company is part of new consortiums and projects that can bring in an additional €51 million or more in future financing.

Frequently asked questions about CPU IP cores

What is Compact, efficient 64-bit RISC-V processor with 5-stage pipeline?

Compact, efficient 64-bit RISC-V processor with 5-stage pipeline is a CPU IP core from Codasip listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

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