Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: PLL

Charter 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation.

Overview

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting different values of DM(5:0) and DN(6:0) according to different REFIN, CLK will be locked at the multiples of input frequency.

Key features

  • Process: Charter 0.13um Dual-Gate (1.2V/3.3V) Nominal with Multi-Vt Process
  • Supply voltage: 1.0v~1.2v~1.32v
  • Current: <2.5mA
  • Operating temperature: - 40c ~ +25c ~ +125c 3. Block Diagram

Specifications

Identity

Part Number
C13V33_PLL_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about PLL IP core

VeriSilicon Launches GCNanoOptimaV, a Next-Generation 2.5D GPU IP for Wearables

Featuring dedicated hardware acceleration engines and an optimized memory architecture, GCNanoOptimaV significantly enhances graphics rendering performance and memory efficiency, enabling richer and more responsive graphical user interfaces (GUIs) while addressing the stringent resource constraints of wearable applications.

Frequently asked questions about PLL IP cores

What is Charter 0.13um 1.2v APLL?

Charter 0.13um 1.2v APLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP