Camera 6/7-mode Combo Receiver - 1G/1.5Gbps

The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification. The CL12684KM4-8-12-16R3AM6-7AIP can change Interface type to same PAD for changing mode.

• MIPI DPHY v1-1 / MIPI CSI / TIA/EIA-644 LVDS / SLVS-400 compliant
• Differential signal of almost CIS serial inputs support
  • 1) sub-LVDS Serial / Parallel
  • 2) mini-LVDS (Reduce Mode LVDS)
  • 3) LVDS
  • 4) HiSPi (SLVS-400, HiVCM)
  • 5) MIPI DPHY
  • 6) CMOS 1.8V
  • 7) CMOS 3.3V (CL12684M4-8-12-16R3AM7AIP SMIC40LL Only)
• Maximum Input Clock Frequency: ~500M/750MHz
• Maximum Input Data Rate: ~1G/1.5Gbps
• Maximum Output Clock Frequency: ~500M/750MHz
• Maximum Output Data Rate: ~500M/750Mbps
• Power Voltage:
  • CL12684K4-8-12-16R3AM6AIP: Analog 2.5V / Digital 1.0V (T55GP)
  • CL12684M4-8-12-16R3AM6-7AIP: Analog 1.8V / Digital 1.1V (T40LP/S40LL)
  • CL12684M4-8-12-16R3AM6AIP: Analog 1.8V / Digital 0.9V (T28HPC/U28HPC)
• Maximum Serial Input Ports(Lanes):
  • CL12684KM4R3AM6-7AIP: Clock 1-port / Data 4-ports (lanes) x1
  • CL12684KM8R3AM6-7AIP: Clock 1-port / Data 4-ports (lanes) x2
  • CL12684KM12R3AM6-7AIP: Clock 1-port / Data 4-ports (lanes) x3
  • CL12684KM16R3AM6-7AIP: Clock 1-port / Data 4-ports (lanes) x4
• Parallel Input 12/14/16bit support for CKIMODE pin (Using CKB only mode)
  • CL12684KM4R3AM6-7AIP: Parallel 8/1012/14/16bit support for using x2/3/4-IP
  • CL12684KM8R3AM6-7AIP: Parallel 8/10/12/14/16bit support for using x1/2-IP
  • CL12684KM12R3AM6-7AIP: Parallel 8/10/12bit support
  • CL12684KM16R3AM6-7AIP: Parallel 8/1012/14/16bit support
• Output Serial Clock Edge Programmable for FRPCK pin
• Output Format 2/4/8bit Selectable for BTSEL[1:0]
• MSB/LSB Selectable for SBSEL pin
• Using for receiver of almost CMOS Image Sensor (Panasonic/Sony/Aptina/OVT/AltaSels/ST-micro e.t.c.)
• Process:
  • CL12684K4-8-12-16R3AM6AIPT055GP: TSMC 55nm Generic Process 1P7M
  • CL12684M4-8-12-16R3AM6/7AIPS040LL: SMIC 40nm Low Leak 1P8M
  • CL12684M4-8-12-16R3AM6AIPT040LP: TSMC 40nm Low Power 1P8M
  • CL12684M4-8-12-16R3AM6AIPT028HPC: TSMC 28nm HPC 1P8M5X2Z
  • -CL12684M4-8-12-16R3AM6AIPU028HPC: UMC 28nm HPC 1P8M0T0F2A0C
• Poly Direction of TSMC/UMC 28nm HPC: South-North
• Various process porting support available ( Please contact us. )
• Supporting Link-layer for CD12684S4-8-12-16LRM3AIP187P5 (CSI2, LVDS, HiSPi Combo) soft macro

• This IP is supported almost CMOS Image Sensor. Thus if when the customer want to use customer's LSI other system set, the customer don't need to change IP, because this IP can change Interface type to same PAD for changing mode pin.
• The system customer can select from many CMOS image sensor for using out IP.
• We are updating CMOS Image Sensor's modelnumber of verify operation for getting information from customer and ourself at all time.
• If the customer need combo Link-layer, we can provide them and can support system.
• We are provided CIS and TX Verilog Model. Thus the customer can confirm function by verilog simulation status.

• Camera Application
• Security Camera
• Mobile-Phone Camera
• DSC(Digital Still Camera)
• Medical Camera
• SLR
• 3D Camera
• Camcorder
• ISP(Image Signal Processer)

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX IC and Board and Datasheet of BOST(Option)
• TX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Combo Link Layer IP and FPGA Board(Option)