Vendor: Curious Corp. Category: MIPI

Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC

The CL12842M8R2JM4TIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) a…

Contact Provider Request Datasheet
TSMC 28nm Silicon Proven View all specifications

Overview

The CL12842M8R2JM4TIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.

The CL12842M8R2JM4TIP2500 is designed to support data rate in excess of maximum 2.5Gbps utilizing SLVS-EC / sub-LVDS / MIPI D-PHY v-1.2/ CMOS 1.8V interface specification. The CL12842M8R2JM4TIP2500 can change Interface type to same PAD for changing mode.

Key features

  • SLVS-EC ver.1.2 / MIPI D-PHY ver.1-2 compliant
  • Supporting for four kind Differential Input Signals
    • 1) SLVS-EC (Maximum 2.4Gbps)
    • 2) sub-LVDS (Maximum 800Mbps)
    • 3) MIPI D-PHY (Maximum 2.5Gbps)
    • 4) CMOS 1.8V (Maximum 166MHz)
  • Xtal Input Clock Frequency Selectable 24MHz / 37.125MHz / 54MHz / 72MHz
  • Maximum Input Clock Frequency ~1.25GHz, Maximum Input Data Transfer Rate ~2.5Gbps
  • Maximum Output Clock Frequency ~312.5MHz
  • Power Supply : Vcc=1.8V (IO and Analog) Vdd=0.9 V (Inside Core)
  • Maximum Lane Number : 8-Lane
  • 10-bit/Lane Parallel Outputs (SLVS-EC)
    • 8-bit/Lane Parallel Outputs (sub-LVDS Serial / MIPI D-PHY)
    • 1-bit/Lane Parallel Outputs (sub-LVDS Parallel)
  • Including Power Down Mode
  • Including "Hi-Z" Detect Circuit for SLVS-EC
  • TSMC 28nm HPC Process 1P10M5X2R (Using of Standard Vth Transistor)
  • Poly Direction: South-North
  • Various process porting support available ( Please contact us. )
  • Supporting Link-layer: CD12842M8LRM3BM4AIP312P5(SLVS-EC/LVDS, CSI2 Combo) soft macro

Benefits

  • This IP is supported almost CMOS Image Sensor. Thus if when the customer want to use customer's LSI other system set, the customer don't need to change IP, because this IP can change Interface type to same PAD for changing mode pin.
  • The system customer can select from many CMOS image sensor for using out IP.
  • We are updating CMOS Image Sensor's modelnumber of verify operation for getting information from customer and ourself at all time.
  • If the customer need combo Link-layer, we can provide them and can support system.
  • We are provided CIS and TX Verilog Model. Thus the customer can confirm function by verilog simulation status.

Applications

  • Camera Application
    • Security Camera
    • Mobile-Phone Camera
    • DSC(Digital Still Camera)
    • Medical Camera
    • SLR
    • 3D Camera
    • Camcorder
  • ISP(Image Signal Processer)

What’s Included?

  • Verilog Model (verilog / vcs)
  • .db file / .lib(Option) file
  • symbol / LVS netlist / Hspice netlist(Option)
  • LEF, layer map file, layout technology file
  • Layout Verification Report (DRC & LVS), Command file
  • Datasheet (This file) /Application Note (Usage connection CIS)
  • Packaging and Layout Guideline / PCB Guideline
  • Static Delay Analysis (STA) Guideline
  • Testing Guideline (Option)
  • TX Verilog Model and Test Vector(Option)
  • CMOS Image Sensor Verilog Models(Option)
  • Combo Link Layer IP(CD12842IP) and FPGA Board(Option)

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm Silicon Proven

Specifications

Identity

Part Number
CL12842M8R2JM4TIP2500
Vendor
Curious Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Curious Corp.
HQ: Japan
Contact Curious Corp.

Learn more about MIPI IP core

M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C

With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about MIPI IP cores

What is Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC?

Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC is a MIPI IP core from Curious Corp. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP