AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
Ethernet
AXI 1G/2.5G Ethernet Subsystem
The AXI Ethernet Subsystem provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.
Overview
The AXI Ethernet Subsystem provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers). The transmit and receive data interface is via the AXI4-Stream interface. This core has been designed incorporating the applicable features described in IEEE Std. 802.3-2012.
Key features
- 10/100/1000 Mbps support
- 2500 Mbps non-processor mode support
- 1588 1-step and 2-step support for UltraScale and 7 series GTX and GTH
- Independent 2K, 4K, 8K, 16K, or 32K Byte TX and RX
- Filtering of "bad" receive frames
- Support for several PHY interfaces
- Media Independent Interface Management access to PHY
- Full Duplex and Half-Duplex support
- Optional support for jumbo frames up to 9K Bytes
- Support for VLAN frames
Specifications
Identity
Part Number
EF-DI-TEMAC-PROJ
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Ethernet IP cores
What is AXI 1G/2.5G Ethernet Subsystem?
AXI 1G/2.5G Ethernet Subsystem is a Ethernet IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.