AVB MAC IIP

AVB MAC core is compliant with IEEE Standard 802.1Q and IEEE 1722 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. AVB MAC IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses

AVB MAC IIP is supported natively in Verilog and VHDL

• Compliant with IEEE 802.3 and IEEE 1722 specifications
• Supports IEEE 802.1 AS for AVB Traffic (gPTP)
• Supports IEEE 1588 - Ingress and egress timestamping per port
• Supports IEEE 802.1Qav - Fowarding and Queuing,Traffic Shaping
• Supports AVB Endpoint talker and/or listener functionality
• Supports IEEE 1722 - Layer 2 Transport Protocol for time sensitive applications
• Supports IEEE 802.1BA – AVB Systems
• Qos Handling based on IEEE 802.1Q
• Support for AVB SR Class A,Class B and Class C traffic - IEEE 802.1Qat Stream Reservation
• Supports IEEE 802.1Qbb - Priority Flow Control (PFC)Supports for MDIO (Clause 22 and Clause 45) Interface
• Configurable Ethernet Ports
• Supports per port rate limiting and port based VLAN support
• Supports MDIO slave and master model as per Clause 22 and Clause 45
• Supports for Programmable Inter Packed Gap(IPG) and Preamble length
• Support GMII/RGMII/MII interface
• FCS generation supported
• Independent TX and RX Maximum Transmission Unit (MTU)
• TSN features can be enabled/disabled independently
• Cut-through support
• Configurable Transmit and Receive FIFOs
• Comprehensive statistics gathering
• Optional DMA support for both transmit and receive side
• In house UNH compliance tested
• Tight integration with SmartDV Ethernet MAC of all Speeds
• In house UNH compliance tested
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The AVB MAC interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.