Vendor: SmartDV Category: Ethernet

AVB MAC IIP

AVB MAC core is compliant with IEEE Standard 802.1Q and IEEE 1722 specification.

Overview

AVB MAC core is compliant with IEEE Standard 802.1Q and IEEE 1722 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. AVB MAC IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses

AVB MAC IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with IEEE 802.3 and IEEE 1722 specifications
  • Supports IEEE 802.1 AS for AVB Traffic (gPTP)
  • Supports IEEE 1588 - Ingress and egress timestamping per port
  • Supports IEEE 802.1Qav - Fowarding and Queuing,Traffic Shaping
  • Supports AVB Endpoint talker and/or listener functionality
  • Supports IEEE 1722 - Layer 2 Transport Protocol for time sensitive applications
  • Supports IEEE 802.1BA – AVB Systems
  • Qos Handling based on IEEE 802.1Q
  • Support for AVB SR Class A,Class B and Class C traffic - IEEE 802.1Qat Stream Reservation
  • Supports IEEE 802.1Qbb - Priority Flow Control (PFC)Supports for MDIO (Clause 22 and Clause 45) Interface
  • Configurable Ethernet Ports
  • Supports per port rate limiting and port based VLAN support
  • Supports MDIO slave and master model as per Clause 22 and Clause 45
  • Supports for Programmable Inter Packed Gap(IPG) and Preamble length
  • Support GMII/RGMII/MII interface
  • FCS generation supported
  • Independent TX and RX Maximum Transmission Unit (MTU)
  • TSN features can be enabled/disabled independently
  • Cut-through support
  • Configurable Transmit and Receive FIFOs
  • Comprehensive statistics gathering
  • Optional DMA support for both transmit and receive side
  • In house UNH compliance tested
  • Tight integration with SmartDV Ethernet MAC of all Speeds
  • In house UNH compliance tested
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Block Diagram

AVB MAC IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The AVB MAC interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
AVB MAC IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Ethernet IP core

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As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Ethernet IP cores

What is AVB MAC IIP?

AVB MAC IIP is a Ethernet IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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