ARINC664 Switch IP Core
ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network.
Overview
ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network. As an implementation of ARINC664 Switch, IP switches/routes messages of different sizes and different time constraints to their destination with a predictable delay. Two level of priority can be applied to the VLs during configuration of the device. Thus, switch can arrange the data queues according to these priorities. Thanks to the AXI4 interface provided with IP Core, error statistics can be fetched to a desired logic and data injection to the network can be accomplished if desired.
Key features
- FUNCTIONAL SPECS
- Supports 128 VLs
- Adjustable BAG values
- Supports 64 Byte as Lmin and 1471 Byte as Lmax
- Adjustable message priority (two classes)
- Multicasting ability
- Outputs error statistic
- INTERFACE SPECS
- AXI4 interface for host communication
- Two ARINC664 Ethernet interfaces
- End System configuration through AXI4 interface
- 100 Mbps/1000 Mbps Ethernet
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Ethernet IP cores
What is ARINC664 Switch IP Core?
ARINC664 Switch IP Core is a Ethernet IP core from ElectraIC listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.