ARINC664 End System IP Core
ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 ne…
Overview
ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network. As an implementation of End System, IP sends the user's messages of different sizes and different time constraints to their destination with a predictable delay. Since the IP core uses the Ethernet interface when connecting to the network, it takes full advantage of the physical layer functions that Ethernet offers. Thanks to the AXI4 interface provided with IP Core, adaptation can be made between any protocol and ARINC664.
Key features
- FUNCTIONAL SPECS
- Supports 32 VLs
- Adjustable BAG values (1ms to 128ms, 125 us to 32 ms)
- Supports 64 Byte as Lmin and 1471 Byte as Lmax
- Redundancy enable/disable capability
- Integrity Checking enable/disable capability
- Outputs error statistic
- INTERFACE SPECS
- AXI4 interface for host communication
- Two ARINC664 Ethernet interface
- End System configuration through AXI4 interface
- 100 Mbps/1000 Mbps Ethernet speed
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Ethernet IP cores
What is ARINC664 End System IP Core?
ARINC664 End System IP Core is a Ethernet IP core from ElectraIC listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.