Linear Regulator IP, Input: 3.3V, Output: 1.2V/1.0V/0.8V, 50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V, 1.0V and 0.8V with 50mA driving capability for each, Istb=130uA, Linear Regulator.
- UMC
- 130nm
- HS
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Linear Regulator IP, Input: 3.3V, Output: 1.2V/1.0V/0.8V, 50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V, 1.0V and 0.8V with 50mA driving capability for each, Istb=130uA, Linear Regulator.
D/A Converter IP, 10 bits, 75MHz, UMC 65nm LL process
3-channel digital-to-Analog converter (Digital-to-Analog converter) with 10-Bit resolution for video application.
D/A Converter IP, 10 bits, 165Msps, UMC 90nm LL process
10-Bit 165MSPS current steering 3-ch Digital-to-Analog converter, UMC 90nm LL Logic(HVT) Low-K process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 36MHz, Output: 500MHz - 1GHz, UMC 90nm SP process
Input 20M-36MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Logic Low-K process.
D/A Converter IP, 16 bits, 96Ksps, UMC 0.25um Logic process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.25um Logic process.
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0.
Audio ADDA IP, 6 bits, 4MHz, UMC 0.18um G2 process
2-channel 4MHz 6-Bit ADC & 8-Bit DAC, UMC 0.18um GII Logic process.
A/D Converter IP, 10 bits, 10Msps, UMC 0.18um G2 process
10-Bit 10MSPS Differential Analog-to-Digital converter, UMC 0.18um GII Logic process.
Voltage Detector IP, 4 Levels, UMC 0.18um G2 process
4-level voltage detector for MP3, UMC 0.18um GII Logic process.
Power on Reset IP, Vrr: 1.2V, Vfr: 1.1V, UMC 0.18um LL process
Vrr=1.2V, Vfr=1.1V, corner type, Power on Reset, UMC 0.18um LL process.
Band Gap IP, Input: 1.2V - 4V, VBG=0.615V, UMC 0.18um LL process
0.18um, LL, bandgap, VBG=0.615 at VCCAH=1.2V~4V, UMC 0.18um LL Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 10MHz - 200MHz, UMC 0.18um G2 process
Input 5M-200MHz, output 10M-200MHz, frequency synthesizable low voltage PLL, UMC 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic proces.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 60MHz - 200MHz, UMC 0.18um G2 process
Input 5M-200MHz, output 60M-200MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
Input 5M-200MHz, output 12.5M-200MHz, frequency synthesizable PLL, UMC 0.18um LL Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process
Input 5M-200MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.15um SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process
Input 5M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.15um SP Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process.
Voltage Detector IP, 4 Levels, UMC 0.13um LL/FSG process
4-level voltage detector, input 1.2V, Ivcca=65uA, UMC 0.13um LL-LVT(FSG) process.