Vendor: Perceptia Devices Category: PLL

All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP

The DeepSub™ pPLL08F is an all digital RF frequency synthesizer PLL featuring industry jitter (sub 300fs), phase noise and compac…

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Samsung 8nm 8LPP View all specifications

Overview

The DeepSub™ pPLL08F is an all digital RF frequency synthesizer PLL featuring industry leading jitter (sub 300fs), phase noise and compact area suitable for RF applications, including 5G and 802.11ax at frequencies up to 8GHz. It is suitable for use as an LO and/or clocking ADCs/DACs with demanding SNR requirements.

pPLL08 uses a LC tank DCO to achieve the performance demands of critical RF systems. It is still low power (< 10mW) and compact compact (< 0.08 sq mm). The all digital architecture minimises interference from other circuits on the same die, making it capable of supporting SNDR better than 60dB.

pPLL08 integrates easily into any SoC design and includes all the views and models required by back end flows.

The pPLL08F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.

pPLL08F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.

Key features

  • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
  • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
  • Small die area (< 0.05 sq mm), using a LC tank oscillator
  • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
  • Reference clock from 5MHz to 1GHz
  • Second-generation digital PLL architecture, providing integer and 24 bit fractional multiplication
  • Primary PLL output running at the main DCO frequency for lowest noise clocking
  • Two further PLL outputs via separate postscalers
    • Post-scalers programmable from 1 to 2,040
  • Lock-detect output
  • PLL output duty cycle better than 49 / 51%
  • Highly testable using industry standard flows
    •   ATPG vectors provided
    •   Specification of functional tests to supplement ATPG testing

Block Diagram

pPLL08-S14LPP block diagram

Benefits

  • Fractional Multiplication with frequencies up to 8GHz
  • Extremely low jitter (< 300fs RMS)
  • Small size  (< 0.05 sq mm)
  • Low Power (< 10mW)
  • Support for many wireless standards including 5G and WiFi
  • Easy integration

Applications

  • RF LO
  • Clock for RF ADC/DAC
  • 5G and LTE radio (3GPP)
  • WiFi Radio (802.11ax)
  • SerDes
  • Optical transceiver

What’s Included?

  • Datasheet
  • Detailed Verilog behavioral model
  • Timing models
  • LEF5.6 abstract for floor planning/chip assembly
  • Integration Guide
  • DFT Guide
  • Integration support
  • Characterization report
  • GDSII layout macrocell
  • CDL netlist for LVS
  • DRC, LVS and SI verification reports
  • Netlist model with accompanying documentation – allowing integration of the module in scan chains

Silicon Options

Foundry Node Process Maturity
Samsung 8nm 8LPP —

Specifications

Identity

Part Number
pPLL08-S14LPP
Vendor
Perceptia Devices
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Perceptia Devices
HQ: Australia
Contact Perceptia Devices

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP?

All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP is a PLL IP core from Perceptia Devices listed on Semi IP Hub. It is listed with support for samsung.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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