AHB External Bus Interface
The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an…
Overview
The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an external device such as an external SRAM or Parallel Flash device.
The number of read wait states, the number of write wait states, and the memory width are all configurable through the APB register interface of the EBI. The EBI allows word, half-word, and byte width addressing to 32-bit, 16-bit, and 8-bit external devices.
The EBI translates AHB writes and reads into writes and reads for the external device. In order to accomplish this task, the EBI is comprised of five major functional blocks: APB Register Interface, Wait State Generation, Address Generation, Control Signal Generation, and Data Steering.
Key features
- Interfaces AHB bus to external SRAM or Parallel Flash devices
- AMBA® AHB Compatible
- Supports 8-bit, 16-bit, and 32-bit external modes
- Supports byte (8-bit), halfword (16-bit), and word (32 bit) internal accesses
- Independent programmable wait states per device interface
- Selects up to 4 external devices
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about On-Chip Bus IP cores
What is AHB External Bus Interface?
AHB External Bus Interface is a Bus Fabric IP core from Silvaco, Inc. listed on Semi IP Hub.
How should engineers evaluate this Bus Fabric?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.