Launching Samsung Foundry IP as Silvaco SIPware - What you Need to Know
Graham Bell, Silvaco
Vendor:
Silvaco, Inc.
Category:
Bus Fabric
AHB External Bus Interface
The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an…
Overview
The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an external device such as an external SRAM or Parallel Flash device.
The number of read wait states, the number of write wait states, and the memory width are all configurable through the APB register interface of the EBI. The EBI allows word, half-word, and byte width addressing to 32-bit, 16-bit, and 8-bit external devices.
The EBI translates AHB writes and reads into writes and reads for the external device. In order to accomplish this task, the EBI is comprised of five major functional blocks: APB Register Interface, Wait State Generation, Address Generation, Control Signal Generation, and Data Steering.
Key features
- Interfaces AHB bus to external SRAM or Parallel Flash devices
- AMBA® AHB Compatible
- Supports 8-bit, 16-bit, and 32-bit external modes
- Supports byte (8-bit), halfword (16-bit), and word (32 bit) internal accesses
- Independent programmable wait states per device interface
- Selects up to 4 external devices
Block Diagram
AHB External Bus Interface block diagram
Specifications
Identity
Part Number
AHB External Bus Interface
Vendor
Silvaco, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United States
Learn more about Bus Fabric IP core
A Time Scaling Theory for Multi-Layer Electronic Systems
For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling.
CSoC Platform / Digital Subsystem IP for IoT
This paper describes a CSoC platform and configurable digital subsystem IP which can be deployed for development of IOT edge devices. The paper encompasses the different attributes of IOT edge device that can cater multiple industry segments, key features and benefits of CSoC platform, components of the digital subsystem IP that enables rapid prototyping of SoCs for IOT applications.
Arteris loses its brain, continues walking
Secure Mobile Payments - Protecting display data in TrustZone-enabled SoCs with the Evatronix PANTA Family of Display Processors
Secure System-on-Chips (SoCs) based on ARM® TrustZone® technology enable both hardware and software components to be isolated as a secure subsystem within a complex SoC and as such focus on processing protected, sensitive and valuable assets, such as payment credentials, whenever these might be endangered with an attack, modification or capture. At the same time the main system software may be an open Rich OS platform that enables downloading and use of arbitrary third-party and non-trusted applications which can gain access to almost all system hardware elements.
SoC low-power verification requires a full-chip solution
The technique that has the highest impact on verification is perhaps the most widely used: power shut off (PSO). Shutting off functional units not currently needed clearly saves both leakage current and dynamic power.
Frequently asked questions about On-Chip Bus IP cores
What is AHB External Bus Interface?
AHB External Bus Interface is a Bus Fabric IP core from Silvaco, Inc. listed on Semi IP Hub.
How should engineers evaluate this Bus Fabric?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.