AFDX 1G MAC IP

SmartDV’s AFDX 1G MAC IP is a silicon-proven, deterministic Ethernet MAC solution purpose-built for safety-critical avionics and aerospace SoC applications. Fully compliant with ARINC 664 Part 7 and IEEE 802.3-2018, it delivers ultra-low latency, high-integrity data transfer across Aircraft Data Networks (ADN) at speeds up to 1 Gbps. Designed as the MAC layer foundation for next-generation avionics systems, it provides the determinism, reliability, and bandwidth control that safety-critical airborne applications demand.

What sets this IP apart is its comprehensive TSN feature set combined with AFDX-specific capabilities. With support for Virtual Link traffic shaping, frame replication and elimination, traffic scheduling, and class-based flow control, it gives avionics SoC teams everything needed to build a fully standards-compliant AFDX end system without compromise. Its in-house UNH compliance testing further validates its readiness for demanding aerospace certification environments.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its fully synthesizable, static synchronous design with scan test readiness enables confident integration and streamlined bring-up across a wide range of process nodes and target applications.

Compliance and Compatibility

• Fully compliant with ARINC 664 Part 7 (AFDX)
• Fully compliant with IEEE 802.3-2022 for 10/100/1000M Ethernet
• Optional support for IEEE 802.1Qbu and IEEE 802.3br frame preemption
• Optional support for IEEE 802.1Qbv and IEEE 802.1Qav traffic scheduling
• Optional support for IEEE 802.1CB frame replication and elimination
• Optional support for IEEE 802.1Q class-based flow control
• In-house UNH compliance tested
• Configurable SoC interface supporting AXI-4 Stream and custom wrappers for seamless integration
• Compatible with ASIC and FPGA design flows across leading foundry process nodes
• Compatible with all major EDA synthesis, simulation, and linting flows

• Full AFDX MAC Support – Complete 10/100/1000M Ethernet MAC implementation compliant with ARINC 664 Part 7 and IEEE 802.3-2018
• Virtual Link Traffic Shaping – Bandwidth Allocation Gap (BAG) enforcement for deterministic, bounded-latency data transfer across Virtual Links
• TSN Feature Support – IEEE 802.1Qbv traffic scheduling, IEEE 802.1Qav credit-based shaping, and IEEE 802.1CB frame replication and elimination for robust time-sensitive networking
• Frame Preemption Support – IEEE 802.1Qbu and IEEE 802.3br Interspersing Express Traffic for ultra-low latency priority frame delivery
• Class-Based Flow Control – IEEE 802.1Q class-based FIFO with support for up to 8 traffic classes for deterministic QoS management
• Ultra-Low Latency Cut-Through – Cut-through switching support for minimal frame delivery latency in time-critical applications
• Comprehensive Statistics – Detailed per-Virtual-Link message count and network statistics per ARINC 664 specification
• Flexible Physical Interface – GMII, RGMII, and MII interface support with configurable TX/RX FIFOs, programmable IPG, and preamble length

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The AFDX interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.