Vendor: Omni Design Technologies, Inc. Category: DAC

12-bit, 2 GSPS High Performance RF DAC in 12nm CMOS

The ODT-DAC-12B2G-12 is a high-performance current steering 12-bit DAC that operates at an update rate of up to 2GSPS.

Contact Provider Request Datasheet
12 Bit TSMC 12nm FFC View all specifications

Overview

The ODT-DAC-12B2G-12 is a high-performance current steering 12-bit DAC that operates at an update rate of up to 2GSPS. The DAC uses a proprietary architecture that reduces harmonic and intermodulation distortions at high output frequency and amplitudes.

The high-performance DAC supports 20mA (maximum) differential output current and achieves up to -149dBm/Hz noise spectral density with excellent SFDR.

The DAC is powered by a 1.8V and 1.2V analog supply, and a 0.8V digital supply.

Key features

  • 12-bit resolution
  • 2GSPS update rate
  • Differential 10mA current (sink) output
  • 1 GHz output bandwidth
  • -149dBm/Hz noise spectral density
  • 70dBc SFDR at FO=50MHz, -1dBFS
  • Embedded direct digital synthesis (DDS) module
  • Functional from -40°C to 125°C

Block Diagram

ODT-DAC-12B2G-12 block diagram

Applications

  • General purpose software defined radio
  • DOCSIS transmitter
  • Cellular base station
  • Broadband communications
  • Wideband satellite transmitter

What’s Included?

  • Datasheet
  • Hard GDS Database (GDSII)
  • Characterization Report (as applicable)
  • Abstract View (LEF) for top level connectivity
  • Spectre Netlist (as needed upon request)
  • Behavioral Model (as appropriate)
  • Integration and Customer Support

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC —

Specifications

Identity

Part Number
ODT-DAC-12B2G-12
Vendor
Omni Design Technologies, Inc.
Type
Silicon IP

Analog

Resolution bits
12 Bit

Provider

Contact Omni Design Technologies, Inc.

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 12-bit, 2 GSPS High Performance RF DAC in 12nm CMOS?

12-bit, 2 GSPS High Performance RF DAC in 12nm CMOS is a DAC IP core from Omni Design Technologies, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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