Prevas acquiring BitSim NOW AB
Prevas has signed an agreement for the acquisition of 100 percent of BitSim NOW AB. BitSim NOW, with its 35 employees, is a consulting firm in Stockholm that focuses on product development.
Vendor:
BitSim NOW
Category:
Ethernet
10 Gb/s full HW stack UDP/IP Transmitter/Receiver
10 Gb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based syste…
Overview
10 Gb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based systems
In application areas such as Data Communication and Imaging, there is a need for increased transfer speeds to handle higher resolutions and higher acquisition rates. This implies more complex solutions in terms of FPGA and board design. This IP core is a real-time offload engine where the communication is processed and accelerated in HW – all the way from UDP to Ethernet Phy. An Ethernet PHY can be integrated in the FPGA enabling a direct connect to the fiber optical SFP+ transceiver.
With data transfer near line rate at theoretical maximum throughput, it is useful for sending large amount of data to a remote PC or host.
In application areas such as Data Communication and Imaging, there is a need for increased transfer speeds to handle higher resolutions and higher acquisition rates. This implies more complex solutions in terms of FPGA and board design. This IP core is a real-time offload engine where the communication is processed and accelerated in HW – all the way from UDP to Ethernet Phy. An Ethernet PHY can be integrated in the FPGA enabling a direct connect to the fiber optical SFP+ transceiver.
With data transfer near line rate at theoretical maximum throughput, it is useful for sending large amount of data to a remote PC or host.
Key features
- Transmits UDP with IP packets up to 10Gb/s, with 10G Ethernet protocol to host
- Receives UDP with IP packets up to 1Gb/s with 10G Ethernet protocol from host
- ARP-table, number of entries can be selected
- Programmable Source/Destination ports and IP/MAC/Default gateway address
- A vendor specific integrated 10 Gb/s PCS/PMA PHY enables a direct connection to SFP+ cages
- Supports the XGMII Interface to the Ethernet PHY
- Payload data is transferred via the AXI4-Stream interface
- Loopback at both AXI-Stream and XGMII interfaces are possible for debugging purposes
- PCIe header interpretation possible, for tunneling of PCIe
- Statistics counters and protocol filters
- Implemented as general VHDL code, independent of FPGA vendor
- Tested with Xilinx Ultrascale & Ultrascale+ and Intel NIC 10GB/s Ethernet board
Block Diagram
Bit-10G-UDP ETHERNET block diagram
What’s Included?
- VHDL source code (readable or encrypted) and testbench with stimuli and checkers
- PC SW driver (Windows, Linux)
- VHDL Simulation Test Benches with BitSim’s Simulation Environment
- User Guide
Specifications
Identity
Part Number
Bit-10G-UDP ETHERNET
Vendor
BitSim NOW
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Sweden
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Frequently asked questions about Ethernet IP cores
What is 10 Gb/s full HW stack UDP/IP Transmitter/Receiver?
10 Gb/s full HW stack UDP/IP Transmitter/Receiver is a Ethernet IP core from BitSim NOW listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.