IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
- IBM
- 65nm
- LPe
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
IBM 65nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
This IP is a programmable Analog PLL suitable for high speed clock generation.
IBM10SF 1.0v/2.5v APLL Brief Specification
This IP is a programmable Analog PLL suitable for high speed clock generation.
The Controller Area Network is a high reliable serial bus protocol defined in the Bosch CAN specification 2.0B.
HDMI 1.4 transmitter IP core is ideal for DVD, Blu-Ray Disc players, set-top boxes, A/V receivers
Analogix offers its silicon-proven HDMI IP cores (digital plus analogix PHY) for integration into customer's system-on-chip produ…
Ethernet AVB Endpoint IP LogiCORE
Ethernet AVB has been merged with the AXI TEMAC IP and AXI Ethernet IP.
The ChipScope PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnect…
The ChipScope OPB IBA core is a specialized Bus Analyzer core designed to debug embedded systems containing the IBM CoreConnect O…
Included with Xilinx ISE Software The Multiplier Accumulator IP core product is a parallel multiplier accumulator module that per…
The LTE Baseband Platform enables customers to more easily exploit the advantages of a 100% Xilinx FPGA baseband implementation, …
The LTE MIMO Decoder provides LTE basestations developers with a optimized and scalable MIMO decode function.
The Universal Serial Bus Device controller (GRUSBDC) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Configurable Multi-Channel Serial Audio Transceiver
The TDM-Pro Configurable Multi-Channel Serial Audio Transceiver Core (CWda26) is part of the AudioWorks™ family of proven audio i…
Serial ATA Dual Host Controller
The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
The VT18PLL500 is a macro cell for clock generation.
LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
V-Trans 's LVDS Display interface IP is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allo…
RSA Public Key Cryptography Exponentiation Accelerator
The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem.
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder
TC4300 is a LDPC decoder designed for China Multimedia Mobile Broadcasting (CMMB) specifications.