High Performance VSB/QAM Demodulator Core
Full digital demodulator supports 8-VSB and 64/256-QAM.
- Modulation Demodulation
- Mature with complete documentation and test vectors
- Now
- ATSC A/53 and ITU-T J.83 An…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
High Performance VSB/QAM Demodulator Core
Full digital demodulator supports 8-VSB and 64/256-QAM.
Synchronous Universal Asynchronous Receiver/Transmitter
The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a micr…
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
H.264 / AVC Baseline Main and High profile decoder
FV264 is a customizable ASIC IP for decoding H.264 compliant streams.
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus.
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus.
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus.
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CP…
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master.
Universal Asynchronous Receiver Transmitter
The macro M16450, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
20mA 3.3V to 1.8V regulator - SMIC 0.18um
3.3V to 1.8V linear voltage regulator for up to 20mA load.
60mA 3.3V to 1.8V regulator - UMC 0.18um
3.3V to 1.8V linear voltage regulator for up to 60mA load.
Power-on reset for 3.3V - SMIC 0.18um
Power-on reset circuit monitoring 3.3V supply
Regulator with low drop-out voltage.
100mA 3.3V to 1.8V regulator - SMIC 0.18um
3.3V to 1.8V linear voltage regulator for up to 100mA.
SHA-1 Secure Hashing Algorithm
The Secure Hashing Algorithm (SHA-1) core was implemented in compliance with Federal Information Processing Standards (FIPS) Publ…
SMIC 0.13um High-Speed Synchronous Two-Port Register File
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File optimized for Semiconductor Manufacturing International Corporation (S…
SMIC 0.13um Synchronous Diffusion ROM
VeriSilicon SMIC 0.13um Synchronous programmable diffusion ROM optimized for Semiconductor Manufacturing International Corporatio…
SMIC 0.13um High-Speed Synchronous Single-Port/Dual-Port SRAM
VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port/Dual-Port SRAM optimized for Semiconductor Manufacturing International…
SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library
VeriSilicon SMIC 0.13um High-Vt High-Density Standard Cell Library developed by VeriSilicon is optimized for Semiconductor Manufa…