Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
- TSMC
- 16nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutio…
The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…
5V ESD Clamp in GlobalFoundries 180nm LPe
A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
Column-parallel high resolution, high speed ADC
Massar is a column-parallel high resolution, high speed ADC tailored to low power consumption and large frame imaging sensors.
LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
Low Power BTDM5.3 Connectivity Transceiver
IP
tRoot V023 FS Hardware Secure Module, ASIL-B compliant (w/ ARC EM22FS)
The ASIL B certified Synopsys tRoot™ Hardware Secure Module (HSM) for Automotive augments its comprehensive root of trust securit…
HMAC-SHA256 cryptographic accelerator
The HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes.
PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
4.3GHz SSCG PLL on TSMC 7nm
The second-generation high-performance RISC-V CPU delivers a major leap in compute capability, designed for deployment across dat…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
The C/D-PHY Combo IP delivers top-tier PPA characteristics and is mass production-proven across multiple customer SoCs.
CXL 3.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
PNG Lossless Compression Encoder
The PNG-E core implements a lossless image compression engine compliant with the Portable Network Graphics (PNG) file format spec…