PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation

The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip interfaces. The PHY’s unique DSP algorithms optimize analog and digital equalization and the patent-pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra low latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enable server and storage applications.

The PHY IP for PCIe 6.x seamlessly interoperates with the Controller IP for PCIe 6.x to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.x and CXL 3.x technologies.

• Supports the latest features of PCIe 6.x and CXL 3.x specifications
• Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
• Delivers more power efficiency across channels with unique DSP algorithms
• Enables near zero link downtime with patent-pending diagnostic features
• Minimizes package crosstalk with placement-aware architecture
• Allows consistent performance across PVT variation with ADC/DSP-based architecture
• Supports PCIe Lane Margining at Receiver
• Supports L0p substate power state, power gating and power island
• Embedded bit error rate tester (BERT), non-destructive internal eye monitor, and first bit error rate (FBER)
• Built-in Self Test vectors, pseudo random bit sequencer (PRBS) generation and checker
• Supports -40°C to 125°C junction temperatures
• Supports flip-chip packaging