Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Erasure code for RAID FEC: The whole operation of e…
- Channel Coding
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Erasure code for RAID FEC: The whole operation of e…
GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation…
224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
The 224G Ethernet PHY IP, an integral part of the high-speed SerDes IP portfolio, meets the growing high bandwidth and low latenc…
Low Dropout (LDO) Capless Regulator on 12nm
The ODT-LDO-IC-250M-12nm is a low dropout (LDO), linear regulator for integration in a SoC.
10M/100M/1G/2.5G Compact Ethernet TSN Switch
Smallest size 1G Ethernet switch IP in the industry targeted for Automotive, Avionics, and Industrial applications The 10M/100M/1…
The RAR-eSR-qLR-ref-[1.62-3.63]-[0.55-2.5].04g embeds and controls two ViC regulators called eSR and qLR.
DC/DC buck converter in TSMC 40ULP supporting 1.8 to 5.5 V input voltage with low quiescent current and high efficiency at light …
DC/DC buck converter in TSMC 40ULP with low quiescent current and high efficiency at light load
DC/DC buck converter in TSMC 40ULP supporting 1.62 to 3.63 V input voltage with low quiescent current and high efficiency at ligh…
24-bit Cap-less ADC 106 dB SNR low power and PLL-less 3 channels
The sADC-uLP-SW1.01 is a mixed (analog and digital) Virtual Component containing six mono ADCs, and additional functions offering…
DC/DC buck converter in GF 22FDX with low quiescent current and high efficiency at light load
DC/DC buck converter in GF 22FDX with low quiescent current and high efficiency at light load.
The MIPI RFFE Slave controller IP is a optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard t…
The first GPU based on Arm’s 5th Gen architecture and designed for flagship smartphones.
High performance-efficient deep learning accelerator for edge and end-point inference
AndesAIRE™ AnDLA™ I350 is a deep learning accelerator (DLA) designed to enable high performance-efficient and cost-sensitive AI s…
Hardware Accelerator for 4D Imaging Radar Solution for Vision 331 and Vision 341 DSPs
Next-generation DSP for embedded vision and AI with millions of units shipped in the market
First DSP for embedded vision and AI with millions of units shipped in the market The Cadence® Tensilica® Vision P6 DSP, introduc…
Unlock High-Speed Data Transfer Between SmartNICs and Host CPU The ULL PCIe DMA Controller is a high-performance, bidirectional d…
MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
Version 1.2 of the D-PHY specification is fully complied with by the MIPI D-PHY Analog RX IP Core.
MIPI D-PHY Tx IP, Silicon Proven in GF 55LP
The D-PHY specification, version 1.2, is completely complied with by the MIPI D-PHY Analog TX IP Core.
64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support.
When you need serious per-core performance, Atrevido brings 4-wide out-of-order execution, and optional tensor math—built to keep models fed and cores busy