Overview
The RAR-eSR-qLR-ref-[1.62-3.63]-[0.55-2.5].04g embeds and controls two ViC regulators called eSR and qLR. The eSR is designed to provide dynamic power from 100 mA to 500 mA, depending on the eSR flavor. The qLR is used for data retention and very low power always-on circuitry (up to 1.0 mA). Both regulators are linked and the RAR embeds a Regulator Control Unit (RCU) that ensures that only one regulator is active at a given moment, while the other regulator output is set to high-impedance state.
The RAR-eSR-qLR-ref-[1.62-3.63]-[0.55-2.5].04g has the possibility to control the booting sequence even when the digital inputs are not yet valid. This function is particularly useful when the RAR supplies the ACU of the SoC. A proper starting sequence is guaranteed even if the ACU is not yet supplied.
The RAR-eSR-qLR-ref-[1.62-3.63]-[0.55-2.5].04g can be used in different modes:
- The Normal Mode: In this mode the eSR is activated and regulates the output. At the same time the qLR is inactivated and its output, VOUT, is set in high-impedance. In this mode the RAR can source up to 100 mA, 200 mA or 500 mA (depending on the embedded eSR).
- The Retention Mode: In this mode the qLR is activated and regulates the output. At the same time the eSR is disactivated and its output, LX, is set in high-impedance.
- The HIZ mode: The outputs of both regulators are in high-impedance state. In this case, the eSR is shut down to reduce the power consumption. HIZ Mode is set by asserting EN and HIZ.
- The Pull-Down Mode, when both regulators are shut down to minimize the power consumption. Both regulator?s outputs are also pulled down to ground. This mode is set by de-asserting EN.
- A internal integrated Local Supply Monitoring (LSM) function is also provided to ensure clean reinitialization if AVD drops below a certain threshold and then restored in a short period of time.
The regulator also features a high impedance (HIZ) mode where its output is kept in a high impedance state to allow the output to be forced via either another regulator, a power switch, or any other mean, provided that the output voltage is kept between 0 V and VAV D.
This product comes with all power pads required for AVD, AVDPWR, LX, VSENSE, GNDSENSE,
and AVS ports, and include their own ESD (Electro-Static Discharge) protection structures.
Learn more about LDO Voltage Regulator IP core
System integrators often encounter problems on application boards too late in the design cycle, when bringing together Virtual Components (ViCs of silicon IPs) into a system. Some ViC performances may be degraded at higher levels (SoC and PCB), and thus the final system does not perform as well as expected. In other words, assembling high-performance ViCs together does not guarantee high-performance SoCs or systems when fundamental integration aspects are not addressed or key issues are violated during the integration process.
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