UART Serial Interface Controller
The CC-UART-AXI is a synthesisable Verilog model of a UART serial interface controller.
- UART
- AXI4-Lite
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UART Serial Interface Controller
The CC-UART-AXI is a synthesisable Verilog model of a UART serial interface controller.
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller.
I2C Master Serial Interface Controller
The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller.
IEEE 802.15.4- 2011 - MAC and PHY
LTIMindtree IEEE 802.15.4 MAC and PHY semiconductor Intellectual Property (IP) is based on IEEE 802.15.4 specification.
Multi-protocol time synchronization IP
Provides sub-microsecond time synchronization, ensuring maximum flexibility for every scenario
IRIG 200-04 compliant time synchronization slave / time receiver for FPGA
IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices.
PTP ordinary (master / time transmitter & slave / time receiver) clock
Provides nanosecond level clock synchronized to network PTP time transmitter.
10M/100M/1G Managed Redundant Switch IP Core
HSR/PRP redundancy + Legacy ethernet ports
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Mas…
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA…
The K-best decoder is part of the MIMO decoder.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations…
DPDK-aware FPGA/GPP data mover
Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software.
The Arm® Cortex®-A55 is the most power efficient mid-range application CPU built on Arm DynamIQ technology.
ARM® Mali™-G72 is the second generation Bifrost-based GPU for High Performance products.
64-bit embedded processor, fully compliant with the RISC-V ISA
SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA.
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.
High Performance NVMe for PCIe-based storage
Typical storage controllers are composed of a communication interface and a Nandflash controller.