The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
- Channel Coding
- Mature
- Now
- IS-GPS-800D
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…
The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC.
IP Set for Miniaturized Telehealth Wearables
HealthIP™ is targeting portable health monitoring (telehealth/telemedicine) and wearable health monitoring devices.
Smart Grid PLC Baseband Processor
The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over po…
Noesis Technologies ntSYNC is a fully programmable component used to achieve time and frequency synchronization in OFDM technolog…
ChaCha20-Poly1305 Crypto Engine
The ChaCha20-Poly1305 Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (AEAD) using th…
Bluetooth Connectivity Platform
The Ceva-Waves Bluetooth platform comprises a comprehensive set of hardware IP, software modules, and radios from Ceva and third-…
Linear Li-Ion Battery Charger - ±1% Accuracy (4.2V) / Up to 1.1A Fast Charge SilTerra 0.18um
This USB/AC Li-Ion battery charger is targeted for portable applications.
Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
DVB S2/S Satellite Tuner SoC White Box IP
This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting.
Scalable RSA and Elliptic Curve Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponen…
14-bit, 50 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B50M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process with an optional input buf…
JPEG Decoder Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
The KJN-F4DEC conform to the JPEG baseline format for decompressing still images.
JPEG Encoder Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
The KJN-F4ENC conform to the JPEG baseline format for compressingstill images.
JPEG Codec Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
The KJN-F4 conform to the JPEG baseline format for compressing/decompressing still images.
The so_ip_sata3_hctrl is a soft core implementation of SATA host controller as defined in the SATA Specification 3.2.
Up to 1,500 MIPS @ 200 Mhz clock frequency for high data processing speed and precise process control The Generic Timer IP module…
Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Re…
10-bit 1-channel 2.6 kSPS SAR ADC
IP 250iHP_ADC_09 is 10-bit 2.6 kSPS ADC employs high-performance single ended successive approximation architecture with embedded…
This IP supports operational data rates 80Mbps to 1.5Gbps per One lane for HS mode, and up to 10Mbps for LP modes transfer rates.