Lattice Semiconductor Corp. IP Cores

Take advantage of the power of FPGA’s parallel processing to implement CNNs.

• NPU

Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolu…

• Channel Coding

The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors,…

• Video Processing

Many new applications such as augmented reality, depth perception and gesture recognition require multiple image sensor interface…

• MIPI

Most off-the-shelf Application Processors use industry standard interfaces such as MIPI CSI-2.

• MIPI

The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets …

• SPI / QSPI XSPI

The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, hig…

• RapidIO

The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2.

• RapidIO

Many digital systems use filters to remove noise, provide spectral shaping, or perform signal detection.

• Filters Transforms

The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with …

• DDR

Most mobile displays use industry standard interfaces such as MIPI DSI for interface connectivity.

• MIPI

Reed-Solomon codes are used to perform Forward Error Correction (FEC).

• Channel Coding

Reed-Solomon codes are used to perform Forward Error Correction.

• Channel Coding

The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and…

• SPI / QSPI XSPI

The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and…

• SPI / QSPI XSPI

Lattice's Quad GbE Over SONET/SDH Bridge is a hard IP Core implemented in two Lattice ORCA4E06 devices that act as a bridge betwe…

• Optical Transport

The second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller…

• SRAM

Platform Management Core IP adds two key power-management functions to Platform Manager: Fault Logging and Enhanced Closed-loop T…

• System Controller

Intel defined the PHY Interface for PCI Express (PIPE) as a standard interface between a PHY device and the Media Access (MAC) la…

• Single-Protocol PHY

PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…

• PCI Express