Vendor: Lattice Semiconductor Corp. Category: SRAM

QDRII + SRAM Controller MACO Core

The second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller…

Overview

The second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller that interfaces with industry standard QDRII and QDRII+ SRAM. The controller can be configured to function in two-word burst or four-word burst modes. It can also be configured to have an 18-bit bus or a 36-bit data bus. The data is transferred on both edges of the clock, doubling the rate of data transfer. Separate read and write data buses again double the data rate.

The QDRII+ IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.

Software Requirements

* ispLEVER version 7.0 or later
* MACO design kit
* MACO license file

Key features

  • Interfaces to industry standard QDRII or QDRII+ SRAM
  • Supports QDRII SRAM memory devices operating up to 250MHz
  • Supports QDRII+ SRAM memory devices operating up to 375MHz (highest speed grade)
  • FPGA can be configured for 18-bit or 36-bit read and write memory data buses (on FPGA, 36-bit or 72-bit data buses)
  • Shared address bus can be configured from 17 bits to 20 bits wide
  • Programmable burst lengths of two or four
  • Maximum read/write blocks of 31 consecutive locations

Block Diagram

PlatformManagerUtilityFunction block diagram

Specifications

Identity

Part Number
PlatformManagerUtilityFunction
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is QDRII + SRAM Controller MACO Core?

QDRII + SRAM Controller MACO Core is a SRAM IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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