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High availability systems such as servers, communication gateways and base stations need to be continuously operational. Once installed in the field, software upgrades handle feature enhancements and bug fixes.
For FPGAs to be part of an ultra-reliable design, designers must protect the valid FPGA configuration used for initialization and prevent SRAM corruption during device operation
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vincent van der Leest, Synopsys
Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.