Vendor: Lattice Semiconductor Corp. Category: NPU

Convolutional Neural Network (CNN) Compact Accelerator

Take advantage of the power of FPGA’s parallel processing to implement CNNs.

Overview

Take advantage of the power of FPGA’s parallel processing to implement CNNs. This IP enables you to implement your own custom network or use many of the commonly used networks published by others.

Our IP provides the flexibility to adjust the number of acceleration engines. By adjusting the numbers of engines and allocated memory, users can trade speed of operation with FPGA’s capacity to obtain the best match for their application.

The CNN Accelerator IP is paired with the Lattice Neural Network Complier Tool. The compiler takes the networks developed in Caffe or TensorFlow, analyzes for resource usage, simulates for performance and functionality, and the compile for the CNN Accelerator IP.

Key features

  • Support convolution layer, max pooling layer, batch normalization layer and full connect layer
  • Configurable bit width of weight (16 bit, 1 bit)
  • Configurable bit width of activation (16/8 bit, 1 bit)
  • Dynamically support 16 bit and 8 bit width of activation
  • Configurable number of memory blocks for tradeoff between resource and performance
  • Configurable number of convolution engines for tradeoff between resource and performance

Block Diagram

Specifications

Identity

Part Number
CNN-ACCEL
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about NPU IP core

Benchmarking an NPU at Scale

With every SDK release, Quadric automatically recompiles and re-profiles the entire model zoo across a broad sweep of hardware configurations. The results land in DevStudio for any SoC architect to explore — no sales call, no handpicked numbers.

Your NPU Learned to Listen

Whisper runs end-to-end on Chimera. Encoder and decoder compiled as native GPNPU kernels, INT4 weights, FP16 attention, top-1 token match against the float32 reference. Scales to four cores with a flag, no recompile.

Heterogeneous NPU Data Movement Tax: Intel's Own Slides Tell the Story

At Quadric, we have long argued that heterogeneous NPU designs — those that stitch together multiple specialized fixed-function engines — carry an unavoidable hidden cost: data has to move. A lot. And data movement burns power, adds latency, and creates silicon-area overhead that scales with every new generation of AI models. Now, Intel has made that case for us.

The Upcoming NPU Shakeout

The IP industry is no stranger to boom and bust cycles, and it looks to be at the crest of another wave.

Frequently asked questions about NPU IP cores

What is Convolutional Neural Network (CNN) Compact Accelerator?

Convolutional Neural Network (CNN) Compact Accelerator is a NPU IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this NPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP