KNiulink Semiconductor Ltd. IP Cores

With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…

• Single-Protocol PHY

With sophisticated architecture and technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high perfo…

• JESD204

With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …

• Single-Protocol PHY

RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture.

• RapidIO

With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…

• Single-Protocol PHY

With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…

• Multi-Protocol PHY

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• Multi-Protocol PHY

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• MIPI PHY

With sophisticated architecture and technology, the Vendor provides LPDDR5 IP solution with high performance and low power.

• LPDDR

With sophisticated architecture and technology, the Vendor provides LPDDR4/4x IP solution with high performance and low power.

• LPDDR

With sophisticated architecture and technology, the Vendor provides LPDDR3 IP solution with high performance and low power.

• LPDDR

With sophisticated architecture and technology, the Vendor provides LPDDR2 IP solution with high performance and low power.

• LPDDR

With sophisticated architecture and technology, the Vendor provides DDR5 IP solution with high performance and low power.

• DDR

With sophisticated architecture and technology, the Vendor provides DDR4 IP solution with high performance and low power.

• DDR

With sophisticated architecture and technology, the Vendor provides DDR3 IP solution with high performance and low power.

• DDR

This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint.

• Single-Protocol PHY

64G SerDes

• Multi-Protocol PHY