Vendor: KNiulink Semiconductor Ltd. Category: DDR

DDR5 IP solution

With sophisticated architecture and technology, the Vendor provides DDR5 IP solution with high performance and low power.

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Overview

With sophisticated architecture and advanced technology, the Vendor provides DDR5 IP solution with high performance and low power. In advanced process nodes, the Vendor could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

Key features

  • Compatible with DDR5 up to 4800Mbps
  • AXI compliant multi-ports, and data width, FIFO depth, command queue depth configurable
  • DFI5.0/4.0 compliant interface between controller and PHY
  • Support ECC (error correcting code)
  • Automatic temperature monitor and refresh rate adjust
  • Support CA, write, read VREF eye training and per-bit training, write leveling training
  • Support Inline BIST and SIPI/LFSR/USER patterns
  • Support DDRPHY loopback test for high speed test
  • Fully PINMUX easy for PKG/PCB routing
  • Support mask write, write/read DBI
  • Support Hardware based DDR frequency switch (DFS), and DFI 1:1/1:2/1:4 programmable with frequency, trade-off latency and power

Block Diagram

DDR5 block diagram

What’s Included?

  • Datasheet (Including Integration Guideline, Interface PINs, clock and reset description, all training flows etc.) (DDRMC & DDRPHY)
  • Register Map files (register address and function description), timing calculation sheet (DDRMC & DDRPHY)
  • Timing lib/db, Layout Frame (.LEF) (DDRPHY)
  • Encrypted RTL and Netlist, SPEF/SDF (DDRPHY)
  • Top Level GDS (DDRPHY)
  • RTL Code & SDC Constraints (DDRMC)
  • Verification environment and cases (testbench, DDRIO Verilog model, initial flow, training flow, bandwidth access, DFT pattern etc. (DDRMC & DDRPHY)

Specifications

Identity

Part Number
DDR5
Vendor
KNiulink Semiconductor Ltd.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

KNiulink Semiconductor Ltd.
HQ: China
KNIULINK is a high-tech semiconductor integrated circuit design company. It is its responsibility to meet the needs of core IP localization. It has deployed SerDes, DDR and other mid-to-high-end IP in mainstream advanced technology; Developing team has long focused on the independent intellectual property research and development of integrated circuit IP cores. Continuous innovation, average work experience of more than ten years, rich accumulation in SerDes IP technology.
Contact KNiulink Semiconductor Ltd.

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is DDR5 IP solution?

DDR5 IP solution is a DDR IP core from KNiulink Semiconductor Ltd. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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