PCI Express (PCIe) IP cores enable high-speed serial communication between components in modern SoC and ASIC designs, delivering scalable bandwidth and low-latency connectivity.
These IP cores support multiple generations including PCIe Gen3, Gen4, Gen5, and Gen6, and include controller, PHY, endpoint, and root complex implementations.
This catalog allows you to compare PCIe IP cores from leading vendors based on data rate, latency, power efficiency, and process node compatibility.
Whether you are designing data center systems, AI accelerators, storage platforms, or high-performance computing systems, you can find the right PCIe IP for your connectivity requirements.
AXI Memory Mapped to PCI Express (PCIe) Gen2
The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express (PCIe) sili…
AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
7 Series Gen2 Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
Xilinx provides a PCI Express Gen3 integrated block for PCI Express® (PCIe) in the Virtex®-7 XT and HT family of FPGAs.
PCIe DMA Controller (Low Latency)
The RapidDMA IP solution offers a fully integrated, -configurable, multi-channel and low latency PCIe-DMA solution.
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.
Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PC…
Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
Xilinx provides a Spartan-6 FPGA Integrated Endpoint solution for PCI Express® (PCIe) to configure the Spartan-6 FPGA Integrated …
Virtex-5 FPGA, Gen1 PCI Express The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-la…
Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
Version 1.8 Now Supports Spartan™-3/3E/3A The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer co…
Virtex-5 Endpoint Block Plus Wrapper for PCI Express (PCIe)
Xilinx provides the ability to configure the FPGA Built-in Endpoint Block for PCIe available in Virtex-5 FPGAs.
R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction…
PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 …
Gen7 supports 128Gbps and backward compatible with previous versions of PCIE.
Ultra Low-Latency IP PCI-express Framework
LeWiz makes available its low-latency PCI-express framework for IP licensing - targeting low-latency applications such as those i…
PCIe Gen4 x8 Lane Endpoint Controller
PCIe Gen4 x8 Lane Endpoint Controller
PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP
PCIe Gen2 x4 Lane Endpoint Controller.
PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP
PCI Express Gen 2 Endpoint Controller.