Vendor: Xilinx, Inc. Category: PCI Express

AXI Memory Mapped to PCI Express (PCIe) Gen2

The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express (PCIe) sili…

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Overview

The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express (PCIe) silicon hard core.  The AXI4 PCIe provides full bridge functionality between the AXI4 architecture and the PCIe network.  The IP is composed of the PCIe core, the GT interface and the AXI4 interface.  The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.

The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TOP packets and the PCIe requests to AXI4 commands.

Key features

  • Support AXI4 memory access to PCIe memory
  • Provide AXI4 master access for PCIe devices
  • Translate AXI4 transactions to appropriate PCIe Transaction Layer Packets (TLP) packets
  • Track and Manage PCIe TLPs that require completion processing
  • Indicate error conditions detected by the PCIe core through interrupt

Specifications

Identity

Part Number
AXI Memory Mapped to PCI Express (PCIe) Gen2
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

Learn more about PCI Express IP core

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Repeatable results with design preservation

Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well. The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations.

Frequently asked questions about PCIe IP cores

What is AXI Memory Mapped to PCI Express (PCIe) Gen2?

AXI Memory Mapped to PCI Express (PCIe) Gen2 is a PCI Express IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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