The I3C Controller is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C connect…
- I2C / I3C
- Silicon Proven
- Now
- MIPI I3C
I2C / I3C IP cores enable standards-based low-speed control and peripheral communication in modern SoC and ASIC designs.
These IP cores support low-speed serial control and sensor communication, including modern I3C enhancements for bandwidth, in-band interrupt support, and dynamic addressing, helping designers integrate interoperable control links across embedded, automotive, industrial, and connectivity-focused systems
This catalog allows you to compare I2C / I3C IP cores from leading vendors based on feature set, latency, power consumption, and process node compatibility.
Whether you are designing sensor hubs, mobile platforms, embedded controllers, or automotive electronics, you can find the right I2C / I3C IP for your application.
The I3C Controller is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C connect…
MIPI I3C (Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication.
I2C Master Serial Interface Controller
The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller.
Two-Wire slave IP for use with the Mentor M8051W and M8051EW
The M2WIS adds two-wire slave capability to M8051W and M8051EW designs.
The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO)…
I2C Controller IP – Master, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
The DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus …
I2C Controller IP – Master / Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
The DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus…
I2C Controller IP – Master, Parameterized FIFO, AXI Bus
The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Master, Parameterized FIFO, AHB Bus
The DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mo…
I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
I2C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
The Microtronix I2C Master/Slave/PIO IP Core is a I2C solution offering three modes of operation and support for standard I2C bus…
Inter-Integrated Circuit (I2C) Master Module
The Inter-IC bus, or I2C bus is a two wire serial bus.
Smart connectivity for mobile, IoT, and automotive innovation The DI3CS device is an I3C Target that complies with the MIPI® Alli…
The proliferation of sensors in mobile wireless and mobile-influenced products has created significant design challenges.
The MIPI I3C host interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compat…
The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.