Overview
NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an IRIG-B004, B005, B006 and B007 Master. The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.
Learn more about IEEE-1588 / PTP IP core
The following sections will take a look at the major Ethernet performance issues and how the extensions address those shortcomings. This will be followed by an overview of the applications of TSN for 5G, industrial automation, automotive invehicle communications and avionics. The paper will conclude with a description of Ethernet TSN solutions offered by Comcores.